SN65LVDS314 Datasheet, PDF (6/44 Pages) Texas Instruments – PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

SN65LVDS314
SLLSE98A – AUGUST 2012 – REVISED SEPTEMBER 2012
Table 1. Pin Description
PIN
SWAP
SIGNAL
PIN
SWAP . SIGNAL
PIN
L
R5
1
22
-
GND_LVDS
43
H
B2
L
R6
2
23
-
VDD_LVDS
44
H
B1
L
R7
3
24
-
VDD_LVDS
45
H
B0
4
-
LS0
25
-
SWAP
46
5
-
VDD
26
-
GND_PLLA
47
6
-
LS1
27
-
VDD_PLLA
48
7
-
VDD_PLLD
28
-
RXEN
49
8
-
GND_PLLD
29
-
VS
50
9
-
VDD_LVDS
30
-
CPE
51
10
-
GND_LVDS
31
-
VDD
52
11
-
D2+
32
-
HS
53
12
-
D2-
33
-
DE
54
13
-
GND_LVDS
34
-
VDD_IO
55
14
-
D1+
35
-
F/S
56
15
-
D1-
36
-
PCLK
57
16
-
GND_LVDS
37
-
GND
58
L
B0
17
-
CLK+
38
59
H
R7
L
B1
18
-
CLK-
39
60
H
R6
L
B2
19
-
GND_LVDS
40
61
H
R5
L
B3
20
-
D0+
41
62
H
R4
L
B4
21
-
D0-
42
63
H
R3
64
SWAP
L
H
L
H
L
H
-
-
-
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
-
-
-
L
H
L
H
L
H
L
H
L
H
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SIGNAL
B5
R2
B6
R1
B7
R0
GND
VDD_IO
CPOL
G0
G7
G1
G6
G2
G5
G3
G4
G4
G3
G5
G2
G6
G1
G7
G0
GND
VDD_IO
VDD
R0
B7
R1
B6
R2
B5
R3
B4
R4
B3
6
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