SN65LVDS314 Datasheet, PDF (16/44 Pages) Texas Instruments – PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

SN65LVDS314
SLLSE98A – AUGUST 2012 – REVISED SEPTEMBER 2012
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INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾
MAX UNIT
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
V_thstby Input voltage common mode threshold to RXEN at V_DD
switch between receive/acquire mode and
standby mode
1.3
0.9×V_DDLVDS
V
V_THL Low-level differential input voltage
V_D0+–V_D0–, V_D1+–V_D1–, V_D2+–V_D2–,
–40
threshold
V_CLK+–V_CLK-
V_THH High-level differential input voltage
threshold
mV
40 _mV
I_I+, I_I–
I_IOFF
R_ID
C_IN
Input leakage current
Power-off input current
Differential input termination resistor value
V_DD=1.95 V; V_I+ = V_I–;
V_I = 0.4 V and V_I = 1.5 V
V_DD=GND; V_I = 1.5V
Input capacitance
Measured between input terminal
and GND
78
100
1
75 _μA
–75 μA
122 Ω
pF
ΔC_IN Input capacitance variation
Within one signal pair
Between all signals
0.2
pF
1
R_BBDC Pull-up resistor for standby detection
LS0, LS1, CPOL, SWAP, RXEN, F/S
21
30
39 kΩ
V_IK Input clamp voltage
I_ICMOS Input current⁽²⁾
C_IN Input capacitance
I_IH
High-level input current
I_IL
Low-level input current
V_IH High-level input voltage
V_IL Low-level input voltage
I_I= –18 mA, V_DD=V_DD(min)
0 V ≤ V_DD≤ 1.95 V; V_I=GND or
V_I=1.95 V
V_IN = 0.7 × V_DD
V_IN = 0.3 × V_DD
-1.2 V
100 nA
2
pF
-200
–200
200
nA
200
0.7×V_DD
0
V_DD
V
0.3×V_DD
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) Do not leave any CMOS Input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic level
V_IH or V_OL while power is supplied to V_DD.
16
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