SM72240 Datasheet, PDF (6/15 Pages) Texas Instruments – SM72240 SolarMagic 5-Pin Microprocessor Reset Circuit

SM72240
SNIS154C – JANUARY 2011 – REVISED APRIL 2013
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The SM72240 reset output ignores short duration glitches on V_CC and MR. See the Applications Information
section for details.
RESET THRESHOLD
The SM72240 is available with a reset voltage of 4.63V or 3.08V which are suitable for monitoring 5.0V or 3.3V
supplies respectively.
MANUAL RESET INPUT (MR)
Many µP-based products require a manual reset capability, allowing the operator to initiate a reset. The MR input
is fully debounced and provides an internal 22 kΩ pull-up. When the MR input is pulled below V_IL (0.25V_CC) for
more than 100 ns, reset is asserted after a typical delay of 2 µs. Reset remains active as long as MR is held low,
and releases after MR rises above V_IH and the reset timeout period expires. Use MR with digital logic to assert
reset or to daisy chain supervisory circuits.
Applications Information
BENEFITS OF PRECISION RESET THRESHOLDS
A microprocessor supply supervisor must provide a reset output within a predictable range of the supply voltage.
A common threshold range is between 5% and 10% below the nominal supply voltage. The SM72240 uses
highly accurate circuitry to ensure that the reset threshold occurs only within this range (for 5.0V and 3.3V
supplies). Table 1 shows how the standard reset threshold applies to 5.0V and 3.3V nominal supply voltages.
Reset Threshold
4.63 ± %
3.08 ± %
Table 1. Monitored Tolerance Table
3.3V
Supply Voltage
91.8–95.2%
5.0V
90.8-94.4%
ENSURING A VALID RESET OUTPUT DOWN TO V_CC = 0V
When V_CC falls below 1V, the SM72240 RESET output is unable to sink the rated current. A high-impedance
CMOS logic input connected to RESET can therefore drift to undetermined voltages. To prevent this situation, a
100kΩ resistor should be connected from the RESET output to ground, as shown in Figure 11.
Figure 11. Circuit for RESET Valid from V_CC = 0V
OPEN DRAIN OUTPUT
An open drain output allows easy paralleling of multiple microprocessor reset circuits without requiring additional
logic gates. Open drain outputs also allow interfacing devices of differing logic levels or families, since the output
pull-up resistor may be connected to any supply voltage up to 5.5V, regardless of V_CC.
The pull up resistor is calculated so that maximum current flow into RESET is less than 10 mA when activated.
The resistor must be small enough so that the leakage current of all connected devices does not create an
excessive voltage drop when the output is not activated. A resistor value of 100 kΩ will generally suffice.
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