OPA827_16 Datasheet, PDF (6/36 Pages) Texas Instruments – Low-Noise, High-Precision, JFET-Input Low-Noise, High-Precision, JFET-Input

OPA827
SBOS376I – NOVEMBER 2006 – REVISED JULY 2016
www.ti.com
6.5 Electrical Characteristics
at V_S = ±4 V to ±18 V, T_A = 25°C, R_L = 10 kΩ connected to midsupply, and V_CM = V_OUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
V_OS
dV_OS/dT
Input offset voltage
Input offset voltage drift
V_S = ±15 V, V_CM = 0 V
T_A = –40°C to 125°C
PSRR
Input offset voltage vs power
supply
T_A = –40°C to 125°C
INPUT BIAS CURRENT
75
150
µV
0.1
2
µV/°C
0.2
1
µV/V
3
±3
±10
pA
I_B
I_OS
NOISE
Input bias current
Input Offset Current
T_A = –40°C to 85°C
T_A = –40°C to 125°C
±500
pA
±5
nA
±3
±10
pA
Input Voltage Noise:
e_n
Input Voltage Noise Density
i_n
Input current noise density
INPUT VOLTAGE RANGE
f = 0.1 Hz to 10 Hz, V_S = ±18 V, V_CM = 0 V
f = 1 kHz, V_S = ±18 V, V_CM = 0 V
f = 10 kHz, V_S = ±18 V, V_CM = 0 V
f = 1 kHz, V_S = ±18 V, V_CM = 0 V
250
nV_PP
4
nV/√Hz
3.8
2.2
fA/√Hz
V_CM
Common-mode voltage
range
(V–) + 3
(V+) – 3
V
(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S < 10 V
104
114
(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S ≥ 10 V
114
126
CMRR
Common-mode rejection
ratio
(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S < 10 V
T_A = –40°C to 125°C
100
dB
(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S ≥ 10 V
T_A = –40°C to 125°C
110
INPUT IMPEDANCE
Differential
10¹³ ∥ 9
Ω ∥ pF
Common-mode
10¹³ ∥ 9
Ω ∥ pF
OPEN-LOOP GAIN
(V–) + 3 V ≤ V_O ≤ (V+) – 3 V, R_L = 1 kΩ
120
126
A_OL
Open-loop voltage gain
(V–) + 3 V ≤ V_O ≤ (V+) – 3 V, R_L = 1 kΩ
T_A = –40°C to 125°C
114
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
G = +1
22
MHz
SR
Slew rate
G = –1
20
28
V/µs
±0.01%, 10-V step, G = –1, C_L = 100 pF
t_S
Settling time
0.00075% (16-bit), 10-V step, G = –1,
C_L = 100 pF
Overload recovery time
Gain = –10
550
ns
850
ns
150
ns
THD+N
Total Harmonic Distortion + ^{G = +1, f = 1 kHz}
Noise
V_O = 3 V_RMS, R_L = 600 Ω
0.00004%
–128
dB
6
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