OPA145 Datasheet, PDF (6/40 Pages) Texas Instruments – High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz JFET Operational Amplifiers

OPA145, OPA2145, OPA4145
SBOS427 – JUNE 2017
7 Specifications
www.ti.com
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
Supply voltage, [(V+) – (V–)]
Signal input pins⁽²⁾
Output short-circuit⁽³⁾
Operating temperature, T_A
Junction temperature, T_J
Storage temperature, T_stg
Dual supply
Single supply
Voltage
Current
MIN
MAX
±20
40
(V–) – 0.5 (V+) + 0.5
±10
Continuous
–55
150
150
–65
150
UNIT
V
mA
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short circuit to V_S / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
7.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
VALUE
2000
750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_S
Supply voltage, [(V+) – (V–)]
T_A
Ambient temperature
Dual supply
Single supply
MIN
±2.25
4.5
–40
NOM
±15
30
25
MAX
±18
36
125
UNIT
V
°C
7.4 Thermal Information: OPA145
THERMAL METRIC⁽¹⁾
D (SOIC)
OPA145
DGK (VSSOP) DBV (SOT)
DSD (SON)
UNIT
8 PINS
8 PINS
5 PINS
8 PINS
R_θJA
R_θJC(top)
R_θJB
Ψ_JT
Ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
136
74
62
19.7
54.8
N/A
143
205
47
°C/W
47
200
47
°C/W
64
113
22
°C/W
5.3
38.2
0.7
°C/W
62.8
104.9
22.6
°C/W
N/A
N/A
9.5
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
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