OPA121 Datasheet, PDF (6/15 Pages) Burr-Brown (TI) – Low Cost Precision Difet OPERATIONAL AMPLIFIER

this may cause a noticeable degradation of offset voltage and
drift.
Static protection is recommended when handling any
precision IC operational amplifier.
GUARDING AND SHIELDING
As in any situation where high impedances are involved,
careful shielding is required to reduce “hum” pickup in input
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA121. To avoid leakage
problems, it is recommended that the signal input lead of the
OPA121 be wired to a Teflon™ standoff. If the OPA121 is
to be soldered directly into a printed circuit board, utmost
care must be used in planning the board layout. A “guard”
pattern should completely surround the high-impedance in-
put leads and should be connected to a low-impedance point
which is at the signal input potential.
The amplifier case should be connected to any input shield
or guard via pin 8. This insures that the amplifier itself is
fully surrounded by guard potential, minimizing both leak-
age and noise pickup (see Figure #2).
If guarding is not required, pin 8 (case) should be connected
to ground.
BIAS CURRENT CHANGE
VERSUS COMMON-MODE VOLTAGE
The input bias currents of most popular BIFET operational
amplifiers are affected by common-mode voltage (Figure 3).
Higher input FET gate-to-drain voltage causes leakage and
ionization (bias) currents to increase. Due to its cascode
input stage, the extremely-low bias current of the OPA121
is not compromised by common-mode voltage.
Teflon™ E.I. du Pont de Nemours & Co.
Non-Inverting
Buffer
8
2
OPA121 ^{6 Out}
In
3
In
Inverting
In
2
OPA121 ^{6 Out}
3
8
8
2
OPA121
3
6 ^Out
TO-99 Bottom View
3
4
5
6
7
2
1
8
Mini-DIP Bottom View
BOARD LAYOUT
8
1
FOR INPUT GUARDING
Guard top and bottom of board.
7
2
Alternate: use Teflon standoff
for sensitive input pins.
6
3
5
4
FIGURE 2. Connection of Input Guard.
80
70 ^{TA = +25°C; curves taken from}
mfg. published typical data
60
LF156/157
50
40
30 ^LF156/157
AD547
LF155
20
10 ^LF155
AD547
0 _OPA121
OPA121
–10 OP-15/16/17 "Perfect Bias Current Cancellation"
–20
–10
–5
0
+5
+10
Common-Mode Voltage (VDC)
FIGURE 3. Input Bias Current vs Common-Mode Voltage.
®
OPA121
6