DS90C383_11 Datasheet, PDF(6/22 Page) Texas Instruments – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

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DS90C383_11 Datasheet, PDF (6/22 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

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Transmitter Switching Characteristics (Continued)

Over recommended operating supply and â40ËC to +85ËC ranges unless otherwise specified

Symbol

Parameter

TPLLS Transmitter Phase Lock Loop Set (Figure 11 )

TPDD

Transmitter Power Down Delay (Figure 15 )

Min Typ Max Units

10 ms

100 ns

Receiver Switching Characteristics

Over recommended operating supply and â40ËC to +85ËC ranges unless otherwise specified

Symbol

CLHT

CHLT

RSPos0

RSPos1

RSPos2

RSPos3

RSPos4

RSPos5

RSPos6

RSKM

RCOP

RCOH

RCOL

RSRC

RHRC

RCCD

RPLLS

RPDD

Parameter

CMOS/TTL Low-to-High Transition Time (Figure 4 )

CMOS/TTL High-to-Low Transition Time (Figure 4 )

Receiver Input Strobe Position for Bit 0 (Figure 18 )

Receiver Input Strobe Position for Bit 1

Receiver Input Strobe Position for Bit 2

Receiver Input Strobe Position for Bit 3

Receiver Input Strobe Position for Bit 4

Receiver Input Strobe Position for Bit 5

Receiver Input Strobe Position for Bit 6

RxIN Skew Margin (Note 5) (Figure 19 )

RxCLK OUT Period (Figure 8)

RxCLK OUT High Time (Figure 8 )

RxCLK OUT Low Time (Figure 8)

RxOUT Setup to RxCLK OUT (Figure 8 )

RxOUT Hold to RxCLK OUT (Figure 8 )

RxCLK IN to RxCLK OUT Delay 25ËC, VCC = 3.3V (Figure 10 )

Receiver Phase Lock Loop Set (Figure 12 )

Receiver Power Down Delay (Figure 16 )

f = 65 MHz

Min Typ Max Units

2.2 5.0 ns

0.7 1.1 1.4 ns

2.9 3.3 3.6 ns

5.1 5.5 5.8 ns

7.3 7.7 8.0 ns

9.5 9.9 10.2 ns

11.7 12.1 12.4 ns

13.9 14.3 14.6 ns

400

7.3 8.6

3.45 4.9

2.5 6.9

2.5 5.7

5.0 7.1 9.0 ns

10 ms

Âµs

Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min

and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows for LVDS interconnect skew, inter-symbol

interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).

AC Timing Diagrams

FIGURE 1. âWorst Caseâ Test Pattern

DS012887-3

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