DAC2932 Datasheet, PDF (6/29 Pages) Burr-Brown (TI) – DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER

DAC2932
SBAS279D − AUGUST 2003 − REVISED JULY 2005
TIMING INFORMATION
t_CP
t_CL
CLK
www.ti.com
t_CH
Data In
[D11:D0]
I−DAC OUT1
I−DAC OUT2
DAC1 (n − 1)
t_S1
DAC2 (n − 1)
t_S2
DAC1 (n)
t_H1
DAC2 (n)
t_H2
DAC1 (n +1)
DAC2 (n + 1)
(n − 2)
t_DO1
(n − 1)
(n)
(n − 2)
(n − 1)
(n)
t_DO2
Figure 1. Timing Diagram of I-DAC
TIMING REQUIREMENTS^(1,2): I-DAC
PARAMETER DESCRIPTION
MIN
TYP
tCP
tCL
tCH
tS1
tS2
tH1
tH2
tDO1(3)
tDO2(3)
Clock cycle time (period)
Clock low time
Clock high time
Data setup time, I-DAC1
Data setup time, I-DAC2
Data hold time, I-DAC1
Data hold time, I-DAC2
Output delay time, I-DAC1
Output delay time, I-DAC2
CS hold time (pulse width)
25
10
10
1
5
1
5
3.35
5
3.35
5
tS1 + tCP
tS2+(tCP/2)
2.49
CS to clock rising or falling edge setup time
0.52
STBY rise time to IOUT
17
PD fall time to IOUT (I-DAC coming out of power-down mode)
22
(1) _{Based on design simulation and characterization; not production tested.}
(2) _{All input signals are specified with tr = tf ≤ 2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2.}
(3) _{Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.}
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
6