DAC2932 Datasheet, PDF (16/29 Pages) Burr-Brown (TI) – DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER

DAC2932
SBAS279D − AUGUST 2003 − REVISED JULY 2005
CHIP SELECT OPERATION
The I−DAC clock is controlled by PD and CS through a
digital clock interface that generates an internal clock
which controls the data latches. Under normal operation
PD and CS are kept low and the internal clock is just a
delayed version of the clock signal present at the CLK pin.
The data for channel 1 and channel 2 are latched by the
rising and falling edges of CLK, respectively. The rising
edge of CLK also causes the DAC to output the previously
latched data pair.
The CS pin can be used to synchronize the latching of data
from a single data bus connected to multiple DAC2932
devices, however in order for this operation to work
correctly the data pairs on the bus have to be scrambled
so that they are arranged correctly at the DAC outputs. The
reason for this is explained in the following:
Figure 28 shows a timing diagram of the CS operation.
When the CS pin is pulled high, the data in the parallel
input port is not latched. The high condition on the CS pin
is latched into the clock interface on the first rising edge of
CLK following the CS edge; this holds the internal clock in
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a high condition, ignoring the CLK edges and thus not
latching the bus data. In order to enable data latching, the
CS pin must be returned to a low state. The change of state
in CS is latched into the clock interface on the first rising
CLK edge; this enables the internal clock which causes the
data in channel 2 to be latched on the first falling edge of
CLK. The next rising edge of CLK causes the DAC to
output the old data from channel 1 and the new data just
latched into channel 2 as well as to latch the new data into
channel 1.
The operation previously described causes problems in
those situations that have two or more DAC2932 devices
sharing the same data bus with each DAC2932 reading
every nth data pair. The (channel1, channel2) data pairs
appearing at the DAC output correspond to (channel1 from
the previous read cycle, channel2 data from the current
read cycle) pairs. In order for the data bus pairs to be
output correctly it is necessary to scramble the (channel1,
channel2) data pairs so that the bus data corresponds to
. . ., channel1, data for other DACs, channel2, . . . for each
DAC2932.
CLK
CS
Data In _{1_0 2_0 1_1 2_1 1_2}
[D11:D0]
2_2 1_3
2_3 1_4
2_4 1_5
I−DAC OUT
1_0
2_1
Figure 28. Timing Diagram of the CS Pin
1_2 2_3
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