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CD54HC377_16 Datasheet, PDF (6/19 Pages) Texas Instruments – High-Speed CMOS Logic Octal D-Type Flip-Flop
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
SYMBOL CONDITIONS (V)
25oC
-40oC TO
85oC
-55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
Maximum Clock Frequency
Power Dissipation Capacitance
(Notes 3, 4)
fMAX
CPD
CL =15pF
CL =15pF
5
-
50
-
-
-
-
-
MHz
5
-
35
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per flip-flop.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
trCL
CLOCK
INPUT
90%
10%
tH(H)
tfCL
50%
tH(L)
DATA
INPUT
tSU(H)
tSU(L)
OUTPUT
tREM
VCC
SET, RESET
OR PRESET
tTLH
90%
tPLH
50%
tTHL
90%
50%
10%
tPHL
IC
CL
50pF
VCC
GND
VCC
50%
GND
GND
trCL
CLOCK
INPUT
2.7V
0.3V
tfCL
1.3V
tH(H)
tH(L)
DATA
INPUT
tSU(H)
1.3V
1.3V
1.3V
tSU(L)
OUTPUT
tREM
3V
SET, RESET
OR PRESET
tTLH
90%
1.3V
tPLH
1.3V
tTHL
90%
1.3V
10%
tPHL
IC
CL
50pF
3V
GND
3V
GND
GND
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6