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CD54HC377_16 Datasheet, PDF (5/19 Pages) Texas Instruments – High-Speed CMOS Logic Octal D-Type Flip-Flop
◁
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Prerequisite for Switching Specifications (Continued)
PARAMETER
Set-up Time,
E, Data to CP
Hold Time,
Data to CP
Hold Time,
E to CP
HCT TYPES
Maximum Clock
Frequency
Clock Pulse Width
Set-up, Time
E, Data to CP
Hold Time,
Data to CP
Hold Time,
E to CP
TEST
VCC
SYMBOL CONDITIONS (V) MIN
tSU
-
2
60
4.5 12
6
10
tH
-
2
3
4.5
3
6
3
tH
-
2
5
4.5
5
6
5
fMAX
tW
tSU
tH
tH
-
4.5 25
-
4.5 20
-
4.5 12
-
4.5
3
-
4.5
5
25oC
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-40oC TO 85oC -55oC TO 125oC
MIN MAX MIN MAX UNITS
75
-
90
-
ns
15
-
18
-
ns
13
-
15
-
ns
3
-
3
-
ns
3
-
3
-
ns
3
-
3
-
ns
5
-
5
-
ns
5
-
5
-
ns
5
-
5
-
ns
-
20
-
16
-
MHz
-
25
-
30
-
ns
-
15
-
18
-
ns
-
3
-
3
-
ns
-
5
-
5
-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
-40oC TO
25oC
85oC
-55oC TO 125oC
TEST
VCC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay (Figure 1)
CP to Q
tPLH,
tPHL
CL = 50pF
2
-
- 175 - 220
-
265
ns
4.5
-
-
35
-
44
-
53
ns
Output Transition Time
(Figure 1)
CL =15pF
CL = 50pF
tTLH, tTHL CL = 50pF
5
-
14
-
-
-
-
-
ns
6
-
-
30
-
37
-
45
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Maximum Clock Frequency
Power Dissipation Capacitance
(Notes 3, 4)
CIN
fMAX
CPD
CL = 50pF
CL =15pF
CL =15pF
-
-
-
10
-
10
-
10
pF
5
-
60
-
-
-
-
-
MHz
5
-
31
-
-
-
-
-
pF
HCT TYPES
Propagation Delay (Figure 1)
CP to Q
Output Transition Time
(Figure 1)
tPLH,
tPHL
CL = 50pF
CL =15pF
tTLH, tTHL CL = 50pF
4.5
-
-
38
-
48
-
5
-
16
-
-
-
-
4.5
-
-
15
-
19
-
57
ns
-
ns
22
ns
Input Capacitance
CIN CL = 50pF
-
-
-
10
-
10
-
10
pF
5
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