ADC122S021_15 Datasheet, PDF (6/28 Pages) Texas Instruments – 2 Channel, 50 ksps to 200 ksps 12-Bit A/D Converter

ADC122S021
SNAS280D – MARCH 2005 – REVISED MARCH 2013
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ADC122S021 TIMING SPECIFICATIONS (continued)
The following specifications apply for V_A = +2.7V to 5.25V, GND = 0V, f_SCLK = 0.8 MHz to 3.2 MHz, f_SAMPLE = 50 ksps to 200
ksps, C_L = 35 pF, Boldface limits apply for T_A = T_MIN to T_MAX: all other limits T_A = 25°C.
Symbol
Parameter
Conditions
Typical Limits ⁽¹⁾ Units
t_CL SCLK Low Pulse Width
t_DIS CS Rising Edge to DOUT High-Impedance
Output Falling
Output Rising
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
0.5 x t_SCLK
1.8
1.3
1.0
1.0
0.3 x
t_SCLK
20
ns (min)
ns (max)
Timing Diagrams
CS
SCLK
DIN
DOUT
Track
Power Up
Hold
Power Down
Track
Power Up
Hold
12 3
4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
4 5 6 7 8 9 10
Control register
b7 b6 b5 b4 b3 b2 b1 b0
Control register
b7 b6 b5 b4 b3 b2 b1 b0
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 1. ADC122S021 Operational Timing Diagram
DB11 DB10 DB9 DB8 DB7
I_OL
200 PA
To Output Pin
C_L
35 pF
1.6V
I_OH
200 PA
Figure 2. Timing Test Circuit
6
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