ADC104S021 Datasheet, PDF (6/27 Pages) Texas Instruments – 4-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter

ADC104S021
SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013
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ADC104S021/ADC104S021Q Timing Specifications⁽¹⁾ (continued)
The following specifications apply for V_A = +2.7V to 5.25V, GND = 0V, C_L = 50 pF, f_SCLK = 0.8 MHz to 3.2 MHz, f_SAMPLE = 50
ksps to 200 ksps, Boldface limits apply for T_A = T_MIN to T_MAX: all other limits T_A = 25°C.
Symbol
Parameter
Conditions
Typical Limits ⁽²⁾ Units
t_H
Data Valid SCLK Hold Time
t_CH SCLK High Pulse Width
t_CL SCLK Low Pulse Width
t_DIS CS Rising Edge to DOUT High-Impedance
Output Falling
Output Rising
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
+3
10
ns (min)
0.5 x t_SCLK
0.5 x t_SCLK
1.7
0.3 x t_SCLK
0.3 x t_SCLK
ns (min)
ns (min)
1.2
20
ns (max)
1.0
1.0
Timing Diagrams
CS
SCLK
DIN
DOUT
Figure 2. Timing Test Circuit
Track
Power Up
Hold
Power Down
Track
Power Up
Hold
12
3
45
6
7
8 9 10 11 12 13 14 15
16 1 2
3
4 5 6 7 8 9 10
Control register
b7 b6 b5 b4 b3 b2 b1 b0
Control register
b7 b6 b5 b4 b3 b2 b1 b0
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB9 DB8 DB7 DB6 DB5
Figure 3. ADC104S021/ADC104S021Q Operational Timing Diagram
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