ADC104S021 Datasheet, PDF (2/27 Pages) Texas Instruments – 4-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter

ADC104S021
SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013
Connection Diagram
CS
V_A
GND
IN4
IN3
1
10
2
9
ADC104S021/
3 _ADC104S021Q 8
4
7
5
6
SCLK
DOUT
DIN
IN1
IN2
Figure 1. 10-Lead VSSOP
See DGK Package
Block Diagram
IN1
.
.
MUX
.
IN4
T/H
GND
10-Bit
SUCCESSIVE
APPROXIMATION
ADC
V_A
GND
CONTROL
LOGIC
SCLK
CS
DIN
DOUT
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Pin No.
ANALOG I/O
4-7
DIGITAL I/O
10
9
8
1
POWER SUPPLY
2
3
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Symbol
Description
IN1 to IN4
SCLK
DOUT
DIN
CS
Analog inputs. These signals can range from 0V to V_A.
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of the
SCLK pin.
Digital data input. The ADC104S021/ADC104S021Q's Control Register is loaded through
this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue
as long as CS is held low.
V_A
GND
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and
bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1
cm of the power pin.
The ground return for supply and signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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