ADC0832CCN Datasheet, PDF (6/40 Pages) Texas Instruments – ADC0831-N/ADC0832-N/ADC0834-N/ADC0838-N 8-Bit Serial I/O A/D Converters with Multiplexer Options

ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N
SNAS531B – AUGUST 1999 – REVISED MARCH 2013
AC Characteristics
The following specifications apply for V_CC = 5V, t_r = t_f = 20 ns and 25°C unless otherwise specified.
Parameter
Conditions
Typ ⁽¹⁾
Tested
Limit ⁽²⁾
Min
10
f_CLK, Clock Frequency
Max
t_C, Conversion Time
Not including MUX Addressing Time
8
Clock Duty Cycle⁽⁴⁾
Min
Max
t_SET-UP, CS Falling Edge or Data Input Valid
to CLK Rising Edge
t_HOLD, Data Input Valid after CLK Rising
Edge
C_L=100 pF
t_pd1, t_pd0—CLK Falling Edge to Output Data
Valid ⁽⁵⁾
Data MSB First
650
Data LSB First
250
t_1H, t_0H,—Rising Edge of CS to Data Output
C_L=10 pF, R_L=10k (See TRI-STATE
Test Circuits and Waveforms)
125
and SARS Hi–Z
C_L=100 pf, R_L=2k
500
C_IN, Capacitance of Logic Input
5
C_OUT, Capacitance of Logic Outputs
5
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Design
Limit ⁽³⁾
400
40
60
250
90
Limit
Units
kHz
kHz
1/f_CLK
%
%
ns
ns
1500
ns
600
ns
250
ns
ns
pF
pF
(1) Typicals are at 25°C and represent most likely parametric norm.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3) Ensured but not 100% production tested. These limits are not used to calculate outgoing quality levels.
(4) A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty
cycle outside of these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1 μs. The
maximum time the clock can be high is 60 μs. The clock can be stopped when low so long as the analog input voltage remains stable.
(5) Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see
ADC0838-N Functional Block Diagram) to allow for comparator response time.
6
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