74AC11374_14 Datasheet, PDF (6/11 Pages) Texas Instruments – OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A − JULY 1987 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C_L = 50 pF
(see Note A)
500 Ω
500 Ω
2 × V_CC
S1
Open
GND
TEST
t_PLH/t_PHL
t_PLZ/t_PZL
t_PHZ/t_PZH
S1
Open
2 × V_CC
GND
LOAD CIRCUIT
Input
t_w
50%
V_CC
50%
0V
VOLTAGE WAVEFORMS
Timing Input
V_CC
50%
t_su
Data Input
50%
0V
t_h
V_CC
50%
0V
VOLTAGE WAVEFORMS
Input
50%
V_CC
50%
0V
In-Phase
Output
t_PLH
t_PHL
Out-of-Phase
Output
50% V_CC
50% V_CC
t_PHL
V_OH
50% V_CC
V_OL
t_PLH
V_OH
50% V_CC
V_OL
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V_CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t_PZL
t_PZH
50%
50%
t_PLZ
50% V_CC
t_PHZ
20% V_CC
50% V_CC
80% V_CC
VOLTAGE WAVEFORMS
V_CC
0V
[ V_CC
V_OL
V_OH
[0V
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_O = 50 Ω, t_r = 3 ns, t_f = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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