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TMS320DM368ZCEDF Datasheet, PDF (59/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)
www.ti.com
OSCIN
TMS320DM368
SPRS668C – APRIL 2010 – REVISED JUNE 2011
Pre-DIV
(Programmable)
PLL
Post-DIV*
PLLM
(Programmable)
PLLEN
1
0
PLLDIV1*
PLLDIV2*
PLLDIV3*
PLLDIV4*
PLLDIV5*
SYSCLK1
(USB Reference Clock)
SYSCLK2 (ARM926EJ-S,
HDVICP Block Clock)
SYSCLK3 (DDR 2x Clock)
SYSCLK4
(Voice Codec Clock)
SYSCLK5 (VENC Clock)
* – Programmable
OSCDIV1*
OBSCLK
(CLKOUT1)
Figure 3-4. PLLC2 Configuration
3.3.5 Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating
Frequencies
Table 3-4 shows the maximum speeds supported for each of the major blocks supported on the different
speed grade devices.
Table 3-4. Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies
ARM926 RISC
Co-Processor (HDVICP)
Co-Processor (MJCP)
DDR2
mDDR
VPSS Logic Block
Peripheral System Bus and EDMA
VPBE-VENC
VPFE
DM368
432 MHz
340 MHz
340 MHz
340 MHz
168 MHz
340 MHz
170 MHz
74.25 MHz
120 MHz
3.3.6 PLL Controller Clocking Configurations Examples
Like the DM365, the DM368 uses two PLLs to generate the two fundamental clocks used on the device.
These two clocks feed two divider blocks which generate all of the functional clocks used by the
peripherals and cores in the DM368. The ARM926 and DDR peripheral in the DM368 are limited to a
maximum clock frequency of 432 MHz and 340 MHz respectively. There are some peripheral clocks on
the DM368 which are required to operate at a specific frequency by functional specification or convention.
These frequencies are detailed in Table 3-5.
Clock
VENC (standard definition)
VENC (high definition)
USB
Voice Codec
Table 3-5. Specific Peripheral Operating Frequencies
Required Frequency (MHz)
27
74.25
36, 24, or 19.2
4.096
Reason
required to generate a valid NTSC signal
required to generate a valid ATSC signal
required by the USB peripheral to generate a 48 MHz USB clock
required to generate a precise 16 kHz audio sample rate
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Device Configurations
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