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TMS320DM368ZCEDF Datasheet, PDF (169/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)
TMS320DM368
www.ti.com
SPRS668C – APRIL 2010 – REVISED JUNE 2011
Table 6-70. Switching Characteristics for I2C Timings(1) (see Figure 6-48)
DEVICE
NO.
PARAMETER
STANDARD
MODE
FAST MODE
MIN MAX MIN MAX
16
tc(SCL)
Cycle time, SCL
10
2.5
17
td(SCLH-SDAL)
Delay time, SCL high to SDA low (for a repeated START condition)
4.7
0.6
18
td(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
4
0.6
19
tw(SCLL)
20
tw(SCLH)
21
td(SDAV-SCLH)
22
tv(SCLL-SDAV)
23
tw(SDAH)
28
td(SCLH-SDAH)
29
Cp
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I2C devices)
Pulse duration, SDA high between STOP and START conditions
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4.7
1.3
4
0.6
250
100
0
0 0.9
4.7
1.3
4
0.6
10
10
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
UNIT
μs
μs
μs
μs
μs
ns
μs
μs
μs
pF
CAUTION
The I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer defined in
the I2C specification. Series resistors may be necessary to reduce noise at the system
level.
SDA
SCL
Stop
23
19
21
20
Start
16
18
18
22
17
Repeated
Start
Figure 6-48. I2C Transmit Timings
28
Stop
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Peripheral Information and Electrical Specifications 169
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