DP83640TVVX Datasheet, PDF (59/137 Pages) Texas Instruments – DP83640 Precision PHYTER - IEEE 1588 Precision Time Protocol Transceiver

DP83640
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SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013
7 Architecture
This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each
operation consists of several functional blocks and is described in the following:
• 100BASE-TX Transmitter
• 100BASE-TX Receiver
• 100BASE-FX Operation
• 10BASE-T Transceiver Module
7.1 100BASE-TX Transmitter
The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble
data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-
TX TP-PMD is integrated, the differential output pins, PMD Output Pair, can be directly routed to the
magnetics.
The block diagram in Figure 7-1 provides an overview of each functional block within the 100BASE-TX
transmit section.
The Transmitter section consists of the following functional blocks:
• Code-Group Encoder and Injection block
• Scrambler block (bypass option)
• NRZ to NRZI Encoder block
• Binary to MLT-3 Converter / Common Driver block
The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for
applications where data conversion is not always required. The DP83640 implements the 100BASE-TX
transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24.
TX_CLK
TXD[3:0]/
TX_EN
DIVIDE
BY 5
4B5B CODE-
GROUP
ENCODER and
INJECTOR
125 MHz CLOCK
5B PARALLEL
TO SERIAL
SCRAMBLER
BP_SCR
MUX
100BASE-TX
LOOPBACK
MLT[1:0]
NRZ TO NRZI
ENCODER
BINARY
TO MLT-3/
COMMON
DRIVER
PMD OUTPUT PAIR
Figure 7-1. 100BASE-TX Transmit Block Diagram
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Architecture
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