TMS320VC5510_17 Datasheet, PDF (58/90 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

Electrical Specifications
5.7.2 Synchronous-Burst SRAM (SBSRAM) Timing
Table 5−7 and Table 5−8 assume testing over recommended operating conditions (see Figure 5−6 and
Figure 5−7).
Table 5−7. Synchronous-Burst SRAM Cycle Timing Requirements
VC5510/5510A-160
NO.
VC5510/5510A-200 _UNIT
MIN
MAX
SB7 tsu(DV-CLKMEMH)
SB8 th(CLKMEMH-DV)
Setup time, read data valid before CLKMEM high
Hold time, read data valid after CLKMEM high
5
ns
2
ns
NO.
SB1
SB2
SB3
SB4
SB5
SB6
SB9
SB10
SB11
SB12
SB13
SB14
SB15
SB16
Table 5−8. Synchronous-Burst SRAM Cycle Switching Characteristics
PARAMETER
VC5510/5510A-160
VC5510/5510A-200
MIN
MAX
td(CLKMEMH-CEL)
td(CLKMEMH-CEH)
td(CLKMEMH-BEV)
td(CLKMEMH-BEIV)
td(CLKMEMH-AV)
td(CLKMEMH-AIV)
td(CLKMEMH-ADSL)
td(CLKMEMH-ADSH)
td(CLKMEMH-OEL)
td(CLKMEMH-OEH)
td(CLKMEMH-DV)
td(CLKMEMH-DIV)
td(CLKMEMH-WEL)
Delay time, CLKMEM high to CEx low
Delay time, CLKMEM high to CEx high
Delay time, CLKMEM high to BEx valid
Delay time, CLKMEM high to BEx invalid
Delay time, CLKMEM high to address valid
Delay time, CLKMEM high to address invalid
Delay time, CLKMEM high to SSADS low
Delay time, CLKMEM high to SSADS high
Delay time, CLKMEM high to SSOE low
Delay time, CLKMEM high to SSOE high
Delay time, CLKMEM high to data valid
Delay time, CLKMEM high to data invalid
Delay time, CLKMEM high to SSWE low
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
td(CLKMEMH-WEH)
Delay time, CLKMEM high to SSWE high
3
6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
58 SPRS076O
June 2000 − Revised September 2007