TMS320VC5510_17 Datasheet, PDF (55/90 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

Electrical Specifications
5.7 Memory Timing
5.7.1 Asynchronous Memory Timing
Table 5−5 and Table 5−6 assume testing over recommended operating conditions (see Figure 5−4 and
Figure 5−5). Note that the asynchronous memory interface is read-only when configured as 8-bit mode.
Asynchronous writes in 8-bit mode are not supported.
Table 5−5. Asynchronous Memory Cycles Timing Requirements
VC5510/5510A-160
NO.
VC5510/5510A-200 _UNIT
MIN MAX
A6 tsu(DV-COH)
Setup time, read data valid before CLKOUT high†
6
ns
A7 th(COH-DV)
Hold time, read data valid after CLKOUT high
0
ns
A10 tsu(ARDY-COH)
Setup time, ARDY valid before CLKOUT high
7
ns
A11 th(COH-ARDY)
Hold time, ARDY valid after CLKOUT high
0
ns
† _{To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold}
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Table 5−6. Asynchronous Memory Cycles Switching Characteristics^‡§
VC5510/5510A-160
NO.
PARAMETER
VC5510/5510A-200 _UNIT
MIN
MAX
A1 td(COH-CEV)
Delay time, CLKOUT high to CEx transition
−2
A2 td(COH-BEV)
Delay time, CLKOUT high to BEx valid
A3 td(COH-BEIV)
Delay time, CLKOUT high to BEx invalid
−2
A4 td(COH-AV)
Delay time, CLKOUT high to address valid
A5 td(COH-AIV)
Delay time, CLKOUT high to address invalid
−2
A8 td(COH-AOEV)
Delay time, CLKOUT high to AOE valid
−2
A9 td(COH-AREV)
Delay time, CLKOUT high to ARE valid
−2
A12 td(COH-DV)
Delay time, CLKOUT high to data valid (write)
A13 td(COH-DIV)
Delay time, CLKOUT high to data invalid (write)
−2
A14 td(COH-AWEV)
Delay time, CLKOUT high to AWE valid
−2
‡ _{The minimum delay is also the minimum output hold after CLKOUT high.}
§ _{All timings referenced to CLKOUT assume CLKOUT represents the internal CPU clock (divide-by-1 mode).}
4 ns
4 ns
ns
4 ns
ns
4 ns
4 ns
4 ns
ns
4 ns
June 2000 − Revised September 2007
SPRS076O
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