PCM1860-Q1 Datasheet, PDF (58/141 Pages) Texas Instruments – Automotive, 4-Channel or 2-Channel, 192-kHz, Audio ADCs

PCM1860-Q1, PCM1861-Q1, PCM1862-Q1
PCM1863-Q1, PCM1864-Q1, PCM1865-Q1
SLASE64A – DECEMBER 2014 – REVISED JUNE 2017
www.ti.com
In master mode, only a 50% duty cycle on the output is possible. This configuration is made by setting
TDM_LRCK_MODE (Page.0 0x0B) to 0.
Typically when interfacing to a DSP, only the rising edge on the first bit of data of the frame is required.
While the device is not transmitting data (but still being clocked), the DOUT pin will be Hi-Z (high impedance) to
allow other devices on the bus to transmit their data.
TDM mode is configured using I2S_FMT (Page.0 0x0B), TDM_LRCK_MODE (Page.0 0x0B), TDM_OSEL
(Page.0 0x0C)
The timing limits for the interface signals are defined by the Serial Audio Data Interface Configuration section
with the addition that the BCK period minimum must at least 1 / (512 × f_S) to ensure that data is clocked in
correctly.
The audio format is shown below. The 24-bit data can fit up to 10 channels of data in a 256x bitclock stream;
however, the I²C-controlled devices only have two possible I²C addresses. The eight channels of audio data
should be no issue.
BCK (fixed at 256 × fS)
Example
24-Bit
TDM Mode
LRCK / Frame Sync
LRCK / Frame Sync
DATA
24-Bit
No Gaps
50% Duty Cycle (Master Mode)
1BCK or 50% Duty Cycle (Slave Mode)
Ch1 data Ch2 data Ch3 data Ch4 data Ch5 data
(24 bits) (24 bits) (24 bits) (24 bits) (24 bits)
Ch6 data
(24 bits)
Ch7 data
(24 bits)
Ch8 data
(24 bits)
Ch9 data Ch10 data EMPTY Ch1 data
xxxx ^{(24 bits) (24 bits) (16 bits) (24 bits)}
BCK (fixed at 256 × fS)
Example
32-Bit
Mode
LRCK / Frame Sync
LRCK / Frame Sync
DATA
24-Bit
8-Bit Gaps
50% Duty Cycle (Master Mode)
1BCK or 50% Duty Cycle (Slave Mode)
Ch1 data 8 Ch2 data 8 Ch3 data 8 Ch4 data 8 Ch5 data 8 Ch6 data 8 Ch7 data 8 Ch8 data 8
(24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits
xx xx xx x
x
x
x
x
Copyright © 2017, Texas Instruments Incorporated
xx xx xx ^{Figure 46. Audio Format for TDM}
x
x
x
x
x
NOTE
TDM mode can only function up to 96 kHz sampling rate when IOVDD is 1.8 V. This is
due to an I/O limitation of 25 MHz at 1.8 V.
58
Submit Documentation Feedback
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1