PCM1860-Q1 Datasheet, PDF (4/141 Pages) Texas Instruments – Automotive, 4-Channel or 2-Channel, 192-kHz, Audio ADCs

PCM1860-Q1, PCM1861-Q1, PCM1862-Q1
PCM1863-Q1, PCM1864-Q1, PCM1865-Q1
SLASE64A – DECEMBER 2014 – REVISED JUNE 2017
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Revision History (continued)
• Added Feature Description section, and moved existing content here ................................................................................ 27
• Changed text in Analog Front End section for clarity ........................................................................................................... 27
• Changed Mic Bias section; internal resistor is a terminating resistor................................................................................... 28
• Deleted Figure 21 and Figure 22 from Mic Bias section ...................................................................................................... 28
• Added note stating that clocks are required to be running in order to change PGA............................................................ 30
• Added text to clarify digital PGA update use in Programmable Gain Amplifier section ....................................................... 30
• Added new paragraph to end of Stereo PCM Sources section............................................................................................ 32
• Changed Figure 30; clock tree updated and corrected ........................................................................................................ 35
• Added new paragraph to target ADC, DSP1 and DSP2 clock rates in Device Clock Distribution and Generation section 35
• Changed Clock Configuration and Selection section; relevant to hardware-controlled devices only .................................. 36
• Added new paragraph regarding register MST_SCK_SRC to Clock Sources for Software-Controlled Devices section .... 36
• Added note ("In Master Mode on..") to Clock Sources for Software-Controlled Devices section ........................................ 37
• Changed Table 7; updated descriptions for clarity ............................................................................................................... 37
• Changed "CLK_DIV_MST_SCK" to "CLK_DIV_SCK_BCK" and "CLK_DIV_MST_BCK" to "CLK_DIV_BCK_LRCK"
in Table 7.............................................................................................................................................................................. 37
• Changed Figure 31; clock tree updated and corrected ........................................................................................................ 37
• Added "Target Clock Rates for ADC, DSP#1 and DSP#2" section ..................................................................................... 38
• Changed Table 10; corrected PLL values by increasing P and R by 1, and corrected DSP1 clock divider values ............ 40
• Changed Table 13; corrected PLL values by increasing P and R by 1, and corrected typo in DSP2 column title.............. 43
• Added text "The clock tree will also need.." to Software-Controlled Devices ADC Non-Audio MCK PLL Mode section..... 44
• Changed PLL condition for D = 0000 to show 1 MHz ≤ (PLLCKIN / P) ≤ 20 MHz and 1 ≤ J ≤ 63 ...................................... 44
• Changed PLL condition for D ≠ 0000 to show 6.667 MHz ≤ (PLLCLKIN / P) ≤ 20 MHz and 4 ≤ J ≤ 11 ............................. 44
• Changed register numbers in Software-Controlled Devices Manual PLL Calculation section to align with the register
numbers in Table 14............................................................................................................................................................. 45
• Changed Clock Halt and Error section; clock error moved to Clocks section, and interrupt capability deleted................... 45
• Added Changing Clock Sources and Sample Rates section ............................................................................................... 46
• Changed Secondary ADC: Energysense and Analog Control section; energysense signal detection not available in
active mode .......................................................................................................................................................................... 47
• Changed text from "control signals up to 1.65 V" to "control signals up to 4.3 V" in the Secondary ADC Analog Input
Range section....................................................................................................................................................................... 48
• Changed section title from "Secondary ADC DC Level Change Detection" to "Secondary ADC Controlsense DC
Level Change Detection" ...................................................................................................................................................... 48
• Added text to the Secondary ADC Controlsense DC Level Change Detection section; controlsense is available in
both active and sleep modes................................................................................................................................................ 48
• Added details to the Secondary ADC Controlsense DC Level Change Detection section regarding how to read
simple 8-bit values from the secondary ADC ....................................................................................................................... 48
• Added new second paragraph to Energysense section ....................................................................................................... 49
• Changed paragraph after Figure 35 in Energysense Signal Loss Flag section to clarify content ....................................... 50
• Changed Digital Decimation Filters section; clarified two different HPFs in the device ....................................................... 52
• Changed text to clarify digital PGA update use in Digital PGA section................................................................................ 52
• Changed Interrupt Controller section; deleted clock error as an interrupt source................................................................ 55
• Changed text after Figure 44 in Interrupt Controller section; clarified INT pins all have same logic signal......................... 55
• Added short description in the DIN Toggle Detection section.............................................................................................. 55
• Added Clearing Interrupts section ........................................................................................................................................ 55
• Changed Digital Audio Output 2 Configuration section; DOUT2 not available in TDM mode, only for 4-ch devices .......... 57
• Added Time Division Multiplex (TDM Support) section ........................................................................................................ 57
• Changed location of timing diagrams to Specifications section, and deleted Interface Timing section ............................... 59
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