LM3S2110 Datasheet, PDF (575/649 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S2110 Microcontroller
Table 17-1. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
46
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
PF0
I/O
TTL
GPIO port F bit 0.
47
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
48
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
49
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
50
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
51
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
52
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
53
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
54
GND
-
Power Ground reference for logic and I/O pins.
55
VDD
-
Power Positive supply for I/O and some logic.
56
VDD
-
Power Positive supply for I/O and some logic.
57
GND
-
Power Ground reference for logic and I/O pins.
58
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
59
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
60
PF2
I/O
TTL
GPIO port F bit 2.
PF1
I/O
TTL
GPIO port F bit 1.
61
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
62
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
63
GND
-
Power Ground reference for logic and I/O pins.
64
RST
I
TTL
System reset input.
65
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
PB0
I/O
TTL
GPIO port B bit 0.
66
CCP0
I/O
TTL
Capture/Compare/PWM 0.
PB1
I/O
TTL
GPIO port B bit 1.
67
CCP2
I/O
TTL
Capture/Compare/PWM 2.
68
VDD
-
Power Positive supply for I/O and some logic.
69
GND
-
Power Ground reference for logic and I/O pins.
PB2
I/O
TTL
GPIO port B bit 2.
70
I2C0SCL
I/O
OD
I²C module 0 clock.
PB3
I/O
TTL
GPIO port B bit 3.
71
I2C0SDA
I/O
OD
I²C module 0 data.
72
PE0
I/O
TTL
GPIO port E bit 0.
73
PE1
I/O
TTL
GPIO port E bit 1.
74
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
75
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
76
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
July 15, 2014
575
Texas Instruments-Production Data