LM3S2110 Datasheet, PDF (185/649 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S2110 Microcontroller
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when a power- on reset or an external reset is
the cause, in which case, all bits other than POR or EXT in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SW
WDT
BOR
POR
EXT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
Bit/Field
31:5
4
3
2
1
0
Name
reserved
SW
WDT
BOR
POR
EXT
Type
RO
R/W
R/W
R/W
R/W
R/W
Reset
0
-
-
-
-
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Software Reset
When set, indicates a software reset is the cause of the reset event.
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
July 15, 2014
185
Texas Instruments-Production Data