TVP3010 Datasheet, PDF (56/91 Pages) Texas Instruments – Video Interface Palette

2.16.3 Cursor Control Register
The cursor control register, see Table 2–21, controls various on-chip cursor functions of the palette. This
register may be accessed by the MPU at any time. Bit 7 of the cursor control register corresponds to data
bus bit 7, index = 06 (hex).
BIT NAME
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1, CCR0
Table 2–21. Cursor Control Register
VALUES
DESCRIPTION
X
Reserved
0: Disable (default) _{Sprite-cursor enable. CCR6 enables (1) or disables (0) the 64 × 64 sprite}
1: Enable
cursor.
0: (default)
1:
Dual-cursor format. CCR5 specifies the display format at the intersection of the
crosshair cursor and the user-defined cursor area (see subsection 2.5.5, and
the cursor-intersection truth table).
0: XGA (default)
1: X-windows
64 × 64 cursor-mode select. CCR4 specifies whether the XGA (0) or
X-windows format is used to interpret the data stored in the 64 × 64 cursor
sprite RAM (see subsection 2.5.2).
0: Color 0 (default) _{Crosshair-color selection. CCR3 specifies whether the crosshair cursor is to}
1: Color 1
be displayed in color 1 (logical 1) or color 0 (logical 0).
0: Disable (default) _{Crosshair-cursor enable. CCR2 specifies whether the crosshair cursor is to be}
1: Enable
displayed in color 1 or not in color 0.
00: 1 pixel (default)
01: 3 pixels
10: 5 pixels
11: 7 pixels
Crosshair thickness. CRR1 and CCR0 specify whether the vertical and
horizontal thickness of the crosshair is one, three, five, or seven pixels. The
segments are centered about the value in the cursor-position (X and Y)
register.
2–40