DAC3484_14 Datasheet, PDF (56/90 Pages) Texas Instruments – Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3484
SLAS749C – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be
just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the
pll_ndivsync_ena bit after resetting the PLL dividers). Besides the t_{s(SYNC_PLL)} and t_{h(SYNC_PLL)} requirement
between SYNC and DACCLK, there is no additional required timing relationship between the SYNC and FRAME
signals or between DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK
and SYNC signals are distributed from device to device with the lowest skew possible.
DACCLKP/N
Outputs
FPGA
SYNCP/N
D[15:0]P/N
FRAMEP/N
Delay 1
DATACLKP/N
DAC3484 DAC1
Clock Generator
Outputs
PLL/
DLL
D[15:0]P/N
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
FRAMEP/N
Delay 2
DATACLKP/N
SYNCP/N
DAC3484 DAC2
Outputs are
Phase Aligned
DACCLKP/N
Figure 62. Synchronization System in Dual Sync Sources Mode with PLL Enabled
B0455-03
The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the
DAC3484 devices have a DACCLK and SYNC signal and the following steps must be carried out on each
device.
1. Start-up the device as described in the power-up sequence. Set the DAC3484 in Dual Sync Sources mode
and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to "1").
2. Reset the PLL dividers with a rising edge on SYNC.
3. Disable PLL dividers resetting.
4. Sync the clock divider and FIFO pointers.
5. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
6. Disable clock divider sync by setting clkdiv_sync_ena to "0" in register config0.
After these steps all the DAC3484 outputs will be synchronized.
MULTI-DEVICE OPERATION: SINGLE SYNC SOURCE MODE
In Single Sync Source mode, the FIFO write and read pointers are reset from the same sync source, either
FRAME or SYNC. Although the FIFO in this mode can still absorb the data delay differences due to variations in
the digital source output paths or board level wiring it is impossible to guarantee data will be read from the FIFO
of different devices simultaneously thus preventing exact phase alignment.
In Single Sync Source mode the FIFO read pointer reset is handoff between the two clock domains (DATACLK
and FIFO OUT CLOCK) by simply re-sampling the write pointer reset. Since the two clocks are asynchronous
there is a small but distinct possibility of a meta-stablility during the pointer handoff. This meta-stability can cause
the outputs of the multiple devices to slip by up to 2 DAC clock cycles.
When the PLL is enabled with Single Sync Source mode, the FIFO read pointer is not synchronized by the
OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section.
56
Submit Documentation Feedback
Product Folder Links: DAC3484
Copyright © 2011–2012, Texas Instruments Incorporated