DAC3484_14 Datasheet, PDF (5/90 Pages) Texas Instruments – Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

www.ti.com
NAME
SCLK
SDENB
SDIO
PIN
NO.
A31
B28
A30
SDO
B27
SLEEP
B40
SYNCP
A5
SYNCN
B5
RESETB
B30
TXENABLE A32
TESTMODE A44
VFUSE
B4
DAC3484
PIN FUNCTIONS (continued)
SLAS749C – MARCH 2011 – REVISED AUGUST 2012
I/O
DESCRIPTION
I Serial interface clock. Internal pull-down.
I Active low serial data enable, always an input to the DAC3484. Internal pull-up.
I/O
Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional 4-pin mode. Internal
pull-down.
O
Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode
(default).
I Active high asynchronous hardware power-down input. Internal pull-down.
I
Optional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100 Ω termination
resistor. If unused it can be left unconnected.
I Optional LVDS SYNC negative input.
I
Active low input for chip RESET, which resets all the programming registers to their default state.
Internal pull-up.
Transmit enable active high input. Internal pull-down.
To enable analog output data transmission, set sif_txenable in register config3 to “1” or pull CMOS
I TXENABLE pin to high.
To disable analog output, set sif_txenable to “0” and pull CMOS TXENABLE pin to low. The DAC
output is forced to midscale.
I This pin is used for factory testing. Internal pull-down. Leave unconnected for normal operation.
I
Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to
DACVDD for normal operation.
Copyright © 2011–2012, Texas Instruments Incorporated
5