LM3S6618_16 Datasheet, PDF (550/692 Pages) Texas Instruments – Stellaris LM3S6618 Microcontroller

Ethernet Controller
Table 15-3. TX & RX FIFO Organization
FIFO Word Read/Write
Sequence
1st
Word Bit Fields
7:0
15:8
2nd
3rd
4th
5th to nth
last
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
TX FIFO (Write)
RX FIFO (Read)
Data Length Least Significant Frame Length Least
Byte
Significant Byte
Data Length Most Significant Frame Length Most Significant
Byte
Byte
DA oct 1
DA oct 2
DA oct 3
DA oct 4
DA oct 5
DA oct 6
SA oct 1
SA oct 2
SA oct 3
SA oct 4
SA oct 5
SA oct 6
Len/Type Most Significant Byte
Len/Type Least Significant Byte
data oct n
data oct n+1
data oct n+2
data oct n+3
FCS 1
FCS 2
FCS 3
FCS 4
Note: If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the
correct CRC. If the CRC bit is set, the Ethernet Controller automatically writes the FCS bytes.
15.3.1.3
Ethernet Transmission Options
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at
the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test
purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing
the CRC bit.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded
into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is
set. This feature can be disabled by clearing the PADEN bit.
The transmitter must be enabled by setting the TXEN bit in the TCTL register.
550
July 16, 2014
Texas Instruments-Production Data