LM3S6618_16 Datasheet, PDF (219/692 Pages) Texas Instruments – Stellaris LM3S6618 Microcontroller

Stellaris^® LM3S6618 Microcontroller
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
reserved
COMP1 COMP0
Type RO
RO
RO
RO
RO
RO
R/W
R/W
RO
Reset
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
reserved I2C1 reserved I2C0
reserved
Type RO
R/W
RO
R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
22
21
reserved
RO
RO
0
0
6
5
SSI1
RO
R/W
0
0
20
19
18
17
16
TIMER3 TIMER2 TIMER1 TIMER0
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
4
SSI0
R/W
0
3
2
reserved
RO
RO
0
0
1
0
UART1 UART0
R/W
R/W
0
0
Bit/Field
31:26
25
24
23:20
19
Name
reserved
COMP1
COMP0
reserved
TIMER3
Type
RO
R/W
R/W
RO
R/W
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
July 16, 2014
219
Texas Instruments-Production Data