DAC39J82 Datasheet, PDF (54/144 Pages) Texas Instruments – Resolution: 16-Bit

DAC39J82
SLASE47 – JANUARY 2015
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7.3.21 JESD204B Pattern Test
The DAC39J82 supports the following test patterns for JESD204B:
• Link layer test pattern
– Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)
– Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)
– Verify repeating initial lane alignment (ILA) sequence
– RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an
amount of time to get an estimate of BER.
• Transport layer test pattern: implements a short transport layer pattern check based on F = 1,2,4 or 8. The
short test pattern has a duration of one frame period and is repeated continuously for the duration of the test.
Refer to JESD204B standard section 5.1.6 for more details.
– F = 1 : Looks for a constant 0xF1.
– F = 2 : Each frame should consist of 0xF1, 0xE2
– F = 4 : Looks for a constant 0xF1, 0xE2, 0xD3, 0xC4
– F = 8 : Each frame should consist of 0xF1, 0xE2, 0xD3, 0xC4, 0xB5, 0xA6, 0x97, 0x80
Users can select to output the internal data (ex, the 8b/10 decoder output, comma alignment output, lane
alignment output, frame alignment output, descrambler output, etc ) of a JESD link for test purpose. See
jesd_testbus_sel for configuration details.
7.3.22 Temperature Sensor
The DAC39J82 incorporates a temperature sensor block which monitors the temperature by measuring the
voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation
(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement
value representing the temperature in degrees Celsius.
The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled
(tsense_sleep = “0” in register config26) a conversion takes place each time the serial port is written or read.
The data is only read and sent out by the digital block when the temperature sensor is read in memin_tempdata
in config7. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the
data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth
SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the
temperature sensor is enabled even when the device is in sleep mode.
In order for the process described above to operate properly, the serial port read from config6 must be done with
an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.
7.3.23 Alarm Monitoring
The DAC39J82 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction
scenario. All the alarm events can be accessed either through the SIP registers and/or through the ALARM pin.
Once an alarm is set, the corresponding alarm bit in register configtbd must be reset through the serial interface
to allow further testing. The set of alarms includes the following conditions:
• JESD alarms
– multiframe alignment_error. Occurs when multiframe alignment fails.
– frame alignment error. Occurs when multiframe alignment fails.
– link configuration error. Occurs when configuration data in ILA sequence does not match programmed
configuration.
– elastic buffer overflow. Occurs when bad RBD value is used causing the elastic buffer to overflow.
– elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed character.
– code synchronization error.
– 8b/10b not-in-table decode error.
– 8b/10 disparity error.
– alarm_from_shorttest. Occurs when the JESD204B interface fails the short pattern test.
• SerDes alarms
– memin_rw_losdct. Occurs when there are loss of signal detect from SerDes lanes.
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