DAC39J82 Datasheet, PDF (4/144 Pages) Texas Instruments – Resolution: 16-Bit

DAC39J82
SLASE47 – JANUARY 2015
www.ti.com
NAME
ALARM
AMUX0
AMUX1
ATEST
DACCLKP
DACCLKN
EXTIO
GND
IFORCE
IOUTAP
IOUTAN
IOUTBP
IOUTBN
IOUTCP
IOUTCN
IOUTDP
IOUTDN
LPF
RBIAS
RESETB
RX0P
RX0N
RX1P
RX1N
RX2P
RX2N
RX3P
PIN
NUMBER
L8
H3
E3
K9
A10
A9
F10
A12, F12, G12,
M12, A11, B11,
C11, D11, E11,
F11, G11, H11,
J11, K11, L11,
M11, C8, D8, E8,
F8, G8, H8, J8,
E7, F7, G7, H7,
E6, F6, G6, H6,
A5, B5, E5, F5,
G5, H5, A4, B4,
M4, B3, C3, L3,
B2, C2, D2, E2,
H2, J2, K2, L2
C5
B12
C12
E12
D12
H12
J12
L12
K12
C9
G10
K8
G1
H1
K1
J1
L1
M1
M3
Pin Functions
I/O
DESCRIPTION
CMOS output for ALARM condition. The ALARM output functionality is defined through the
O config7 register. Default polarity is active high, but can be changed to active high via config0
alarm_out_pol control bit. If not used it can be left open.
I/O Analog test pin for SerDes, Lane 0 to Lane 3. It can be left open if not used.
I/O Analog test pin for SerDes, Lane 4 to Lane 7. It can be left open if not used.
I/O Analog test pin for DAC, references and PLL. It can be left open if not used.
Positive LVPECL clock input for DAC core with V_cm = 0.5V. It can be PLL reference clock or
I external DAC sampling rate clock. If not used, DACCLK is self-biased with 100mV differential
at V_cm = 0.5V.
I Complementary LVPECL clock input for DAC core. (see the DACCLKP description)
Used as external reference input when internal reference is disabled through config27
I/O
extref_ena = ‘1’. Used as internal reference output when config27 extref_ena = ‘0’ (default).
Requires a 0.1 μF decoupling capacitor to analog GND when used as reference output. It can
be left open if not used.
I These pins are ground for all supplies.
I/O Analog test pin for on chip parametric. It can be left open if not used.
O A-Channel DAC current output. Must be tied to GND if not used.
O A-Channel DAC complementary current output. Must be tied to GND if not used.
O B-Channel DAC current output. Must be tied to GND if not used.
O B-Channel DAC complementary current output. Must be tied to GND if not used.
O C-Channel DAC current output. Must be tied to GND if not used.
O C-Channel DAC complementary current output. Must be tied to GND if not used.
O D-Channel DAC current output. Must be tied to GND if not used.
O D-Channel DAC complementary current output. Must tied to GND if not used.
I/O External PLL loop filter connection. It can be left open if not used.
O
Full-scale output current bias. Change the full-scale output current through coarse_dac(3:0).
Expected to be 1.92kΩ to GND.
I
Active low input for chip RESET, which resets all the programming registers to their default
state. Internal pull-up. It can be left open if not used.
I
CML SerDes interface lane 0 input, positive, expected to be AC coupled. It can be left open if
not used.
I
CML SerDes interface lane 0 input, negative, expected to be AC coupled. It can be left open if
not used.
I
CML SerDes interface lane 1 input, positive, expected to be AC coupled. It can be left open if
not used.
I
CML SerDes interface lane 1 input, negative, expected to be AC coupled. It can be left open if
not used.
I
CML SerDes interface lane 2 input, positive, expected to be AC coupled. It can be left open if
not used.
I
CML SerDes interface lane 2 input, negative, expected to be AC coupled. It can be left open if
not used.
I
CML SerDes interface lane 3 input, positive, expected to be AC coupled. It can be left open if
not used.
4
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