ADS8588S Datasheet, PDF (53/63 Pages) Texas Instruments – 16-Bit, 200-kSPS, 8-, 6- and 4-Channel, Simultaneous-Sampling ADCs with Bipolar Inputs on a Single Supply

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11 Layout
ADS8588S, ADS8586S, ADS8584S
SBAS642 – DECEMBER 2016
11.1 Layout Guidelines
Figure 90 and Figure 91 illustrate a PCB layout example for the ADS8588S, ADS8586S, and ADS8584S.
• Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are
kept away from the digital lines. This layout helps keep the analog input and reference input signals away
from the digital noise. In this layout example, the analog input and reference signals are routed on the left
side of the board and the digital connections are routed on the right side of the board.
• Using a single common ground plane is strongly recommended. For designs requiring a split analog and
digital ground planes, the analog and digital ground planes must be at the same potential joined together in
close proximity to the devices.
• Power sources to the ADS8588S must be clean and well-bypassed. As a result of dynamic currents during
conversion, each AVDD must have a decoupling capacitor to keep the supply voltage stable. Use wide traces
or a dedicated analog supply plane to minimize trace inductance and reduce glitches. Using a 1-μF, X7R-
grade, 0603-size ceramic capacitor is recommended in close proximity to each analog (AVDD) supply pins.
Bypass capacitors for AVDD pins 1 and 48 are located on the top layer; see Figure 90. AVDD supply pins 37
and 38 are connected to bypass capacitors in the bottom layer using an isolated via (1); see Figure 91. A
separate via (2) is used to connect the bypass capacitor to the AVDD plane.
• For decoupling the digital (DVDD) supply pin, a 1-μF, X7R-grade, 0603-size ceramic capacitor is
recommended. The DVDD bypass capacitor is located in the bottom layer; see Figure 91.
• REFCAPA and REFCAPB must be shorted together and decoupled to REFGND using a 10-μF, X7R-grade,
0603-size ceramic capacitor placed in close proximity to the pins of the device. This capacitor is placed on
the top layer and directly connected to the pins of the device. Avoid placing vias between the REFCAPA,
REFCAPB pins and the decoupling capacitor.
• The REFIN/REFOUT pin also must be decoupled to REFGND with a 10-μF, X7R-grade, 0603-size ceramic
capacitor if the internal reference of the device is used. The capacitor must be placed on the top layer in
close to the device pin. Avoid placing vias between the REFIN/REFOUT pin and the decoupling capacitor.
• The REGCAP1 and REGCAP2 pins must be decoupled to GND using a separate 1-μF, X7R-grade, 0603-size
ceramic capacitor on each pin.
• All ground pins (AGND) must be connected to the ground plane using short, low-impedance paths and
independent vias to the ground plane. Connect REFGND to the common GND plane.
• For the optional channel input low-pass filters, ceramic surface-mount capacitors, COG (NPO) ceramic
capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic
capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
11.2 Layout Example
Figure 90 and Figure 91 illustrate a recommended layout for the ADS8588S along with proper decoupling and
reference capacitor placement and connections.
Copyright © 2016, Texas Instruments Incorporated
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