ADS8588S Datasheet, PDF (41/63 Pages) Texas Instruments – 16-Bit, 200-kSPS, 8-, 6- and 4-Channel, Simultaneous-Sampling ADCs with Bipolar Inputs on a Single Supply

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ADS8588S, ADS8586S, ADS8584S
SBAS642 – DECEMBER 2016
8.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
The ADS8588S, ADS8586S, and ADS8584S allow two sets of analog input channels to be simultaneously
sampled. In order to do so, the CONVSTA and CONVSTB signals must be separate control inputs (as shown in
Figure 68) and the devices must not operate in any oversampling mode. Electrical grid relay protection is an
application that can benefit from being able to sample the inputs in two groups. The delay of the signal through
the voltage channels is often different from the delay on the channels measuring current. The difference in delay
created by the voltage and current signal paths can be corrected by adjusting the sampling of the two groups of
inputs (voltage and current) to the devices.
The timing diagram shown in Figure 68 shows the sequence of events described in this section.
CONVSTA
CONVSTB
BUSY
CS and RD
DB[15:0]
AIN_1
AIN_2
AIN_7
AIN_8
FRSTDATA
1a
1b
23
4
Figure 68. Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram
There are four events that describe the internal operation of the devices when pairs of input channels are
simultaneously sampled and the data are read back. These events are:
• Event 1(a): A rising edge on the CONVSTA signal initiates simultaneous sampling of the first set of analog
input channels (channels 1-4 for the ADS8588S, channels 1-3 for the ADS8586S, and channels 1-2 for the
ADS8584S). The sampling circuits on the first set of analog input channels enter hold mode and the input
signals on these channels are sampled at the same instant. The ADC does not begin conversion until the
input signals on the second set of channels are sampled.
• Event 1(b): A rising edge on the CONVSTB signal initiates simultaneous sampling of the second set of
analog input channels (channels 5-8 for the ADS8588S, channels 4-6 for the ADS8586S, and channels 3-4
for the ADS8584S). The sampling circuits for the second set of analog input channels enter hold mode and
the input signals on these channels are sampled at the same instant. When the rising edges of both the
CONVSTA and CONVSTB signals have occurred, the ADC converts all sampled signals using a precise, on-
chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes high and
remains high through a maximum-specified conversion time of t_CONV (see the Timing Requirements: CONVST
Control table).
• Event 2: Same as event 2 in the Simultaneous Sampling on All Input Channels section.
• Event 3: Same as event 3 in the Simultaneous Sampling on All Input Channels section.
• Event 4: Same as event 4 in the Simultaneous Sampling on All Input Channels section.
Note that events 1(a), 1(b), and 2 are common to all interface modes of operation (parallel, serial, or parallel
byte).
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