TLV320AIC3104_12 Datasheet, PDF (52/91 Pages) Texas Instruments – LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

TLV320AIC3104
SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010
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BIT READ/
WRITE
D7
R/W
D6–D3 R/W
D2
R/W
D1–D0 R/W
Page 0/Register 22: MIC1RP/LINE1RP to Right-ADC Control Register
RESET
VALUE
DESCRIPTION
0
MIC1RP/LINE1RP Single-Ended vs Fully Differential Control. If MIC1RP/LINE1RP is selected to both left-
and right-ADC channels, both connections must use the same configuration (single-ended or fully
differential mode).
0: MIC1RP/LINE1RP is configured in single-ended mode.
1: MIC1RP/LINE1RP and MIC1RM/LINE1RM are configured in fully differential mode.
1111
MIC1RP/LINE1RP Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1R to the right-
ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1R is not connected to the right-ADC PGA.
0
Right-ADC Channel Power Control
0: Right-ADC channel is powered down.
1: Right-ADC channel is powered up.
00
Right-ADC PGA Soft-Stepping Control
00: Right-ADC PGA soft-stepping at once per sample period
01: Right-ADC PGA soft-stepping at once per two sample periods
10–11: Right-ADC PGA soft-stepping is disabled.
BIT
D7–D0
READ/
WRITE
R/W
RESET
VALUE
0111 1000
Page 0/Register 23: Reserved Register
DESCRIPTION
Reserved. Do not write to this register.
BIT READ/
WRITE
D7
R/W
D6–D3 R/W
D2–D0 R
Page 0/Register 24: MIC1LP/LINE1LP to Right-ADC Control Register
RESET
VALUE
DESCRIPTION
0
MIC1LP/LINE1LP Single-Ended vs Fully Differential Control. If MIC1LP/LINE1LP is selected to both left-
and right-ADC channels, both connections must use the same configuration (single-ended or fully
differential mode).
0: MIC1LP/LINE1LP is configured in single-ended mode.
1: MIC1LP/LINE1LP and MIC1LM/LINE1LM are configured in fully differential mode.
1111
MIC1LP/LINE1LP Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1L to the right-
ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1L is not connected to the right-ADC PGA.
000
Reserved. Write only zeros to these bits.
52
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