TLV320AIC3104_12 Datasheet, PDF (34/91 Pages) Texas Instruments – LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

TLV320AIC3104
SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010
www.ti.com
DELTA-SIGMA AUDIO DAC
The stereo audio DAC incorporates a third-order multi-bit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise
shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by a
continuous-time RC filter. The analog FIR operates at a rate of 128 f_S(ref) (6.144 MHz when f_S(ref) = 48 kHz,
5.6448 MHz when f_S(ref) = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive
clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.
AUDIO DAC DIGITAL VOLUME CONTROL
The audio DAC includes a digital volume control block which implements a programmable digital gain. The
volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, or set to mute, independently for each
channel. The volume level of both channels can also be changed simultaneously by the master volume control.
Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by one step
per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed
to one step per two input samples through a register bit.
Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be
important if the host wishes to mute the DAC before making a significant change, such as changing sample
rates. In order to help with this situation, the device provides a flag back to the host via a read-only register bit
that alerts the host when the part has completed the soft-stepping and the actual volume has reached the
desired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is
enabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When this
flag is set, the internal soft-stepping process and power-down sequence is complete, and the MCLK can then be
stopped if desired.
The TLV320AIC3104 also includes functionality to detect when the user changes the selection of de-emphasis or
digital audio processing functionality. When the new selection is detected, the TLV320AIC3104 (1) soft-mutes the
DAC volume control, (2) changes the operation of the digital effects processing to match the new selection, and
(3) soft-unmutes the device. This avoids any possible pop/clicks in the audio output due to instantaneous
changes in the filtering. A similar algorithm is used when first powering up or powering down the DAC. The circuit
begins operation at power up with the volume control muted, then soft-steps it up to the desired volume level. At
power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.
INCREASING DAC DYNAMIC RANGE
The TLV320AIC3104 allows trading off dynamic range with power consumption. The DAC dynamic range can be
increased by writing to page 0, register 109, bits D7–D6. The lowest DAC current setting is the default, and the
dynamic range is displayed in the AUDIO DAC – Differential Line Output section of the Electrical Characteristics
table. Increasing the current can increase the DAC dynamic range by up to 1.5 dB.
ANALOG OUTPUT COMMON-MODE ADJUSTMENT
The output common-mode voltage and output range of the analog output are determined by an internal band-gap
reference, in contrast to other codecs that may use a scaled version of the analog supply. This scheme is used
to reduce the coupling of noise that may be on the supply (such as 217-Hz noise in a GSM cellphone) into the
audio signal path.
However, due to the possible wide variation in analog supply range (2.7 V–3.6 V), an output common-mode
voltage setting of 1.35 V, which would be used for a 2.7 V supply case, would be overly conservative if the
supply is actually much larger, such as 3.3 V or 3.6 V. In order to optimize device operation, the TLV320AIC3104
includes a programmable output common-mode level, which can be set by register programming to a level most
appropriate to the actual supply range used by a particular customer. The output common-mode level can be
varied among four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to
1.8 V (most appropriate for high supply ranges, near 3.6 V). Note that the recommended DVDD voltage is
dependent on the CM setting, as shown in Table 4.
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