TMS320VC5509A_14 Datasheet, PDF (51/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.7 System Register
The system register (SYSR) provides control over certain device-specific functions. The register is located
at port address 07FDh.
15
8
Reserved
7
3
2
0
Reserved
CLKDIV
R/W
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−16. System Register Bit Locations
NUMBER
15−3
BIT
NAME
Reserved
CLKDIV
2−0
Table 3−17. System Register Bit Fields
FUNCTION
These bits are reserved and are unaffected by writes.
CLKOUT Divide Factor. Allows the clock present on the CLKOUT pin to be a divided-down version
of the internal CPU clock. This field does not affect the programming of the PLL.
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
000 = CLKOUT represents the CPU clock divided by 1
001 = CLKOUT represents the CPU clock divided by 2
010 = CLKOUT represents the CPU clock divided by 4
011 = CLKOUT represents the CPU clock divided by 6
100 = CLKOUT represents the CPU clock divided by 8
101 = CLKOUT represents the CPU clock divided by 10
110 = CLKOUT represents the CPU clock divided by 12
111 = CLKOUT represents the CPU clock divided by 14
3.8 USB Clock Generation
The USB module can be clocked from either an Analog Phase-Locked Loop (APLL) or a Digital Phase-Locked
Loop (DPLL). The APLL is the recommended USB clock source due to better noise tolerance and less
long-term jitter than the DPLL. To maintain the backward compatibility, the DPLL is the power-up default clock
source for the USB module.
CLKIN
USB
APLL
USB
DPLL
1
USB Module Clock
(48.0 MHz)
0
PLLSEL
Figure 3−17. USB Clock Generation
November 2002 − Revised January 2008
SPRS205K
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