TMS320VC5509A_14 Datasheet, PDF (26/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
FUNCTION
BK‡
RESET
CONDITION
TIMER SIGNALS
TIN/TOUT0
Timer0 Input/Output. When output, TIN/TOUT0 signals a pulse or a
change of state when the on-chip timer counts down past zero. When
input, TIN/TOUT0 provides the clock source for the internal timer module.
I/O/Z
H
At reset, this pin is configured as an input.
NOTE: Only the Timer0 signal is brought out. The Timer1 signal is
terminated internally and is not available for external use.
Input
REAL-TIME CLOCK
RTCINX1
I Real-Time Clock Oscillator input
Input
RTCINX2
SDA
SCL
O Real-Time Clock Oscillator output
I2C
I/O/Z I2C (bidirectional) data. At reset, this pin is in high-impedance mode.
H
I/O/Z I2C (bidirectional) clock. At reset, this pin is in high-impedance mode.
H
Output
Hi-Z
Hi-Z
MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS
CLKR0
McBSP0 receive clock. CLKR0 serves as the serial shift clock for the serial
I/O/Z
H
Hi-Z
port receiver. At reset, this pin is in high-impedance mode.
DR0
I McBSP0 receive data
FS
Input
FSR0
McBSP0 receive frame synchronization. The FSR0 pulse initiates the data
I/O/Z
Hi-Z
receive process over DR0. At reset, this pin is in high-impedance mode.
CLKX0
McBSP0 transmit clock. CLKX0 serves as the serial shift clock for the
I/O/Z
H
serial port transmitter. The CLKX0 pin is configured as input after reset.
Input
McBSP0 transmit data. DX0 is placed in the high-impedance state when
DX0
O/Z
Hi-Z
not transmitting, when RESET is asserted, or when OFF is low.
FSX0
McBSP0 transmit frame synchronization. The FSX0 pulse initiates the
I/O/Z
data transmit process over DX0. Configured as an input following reset.
Input
McBSP1 receive clock or MultiMedia Card/Secure Digital1
S10
I/O/Z
command/response. At reset, this pin is configured as McBSP1.CLKR.
McBSP1 receive clock. McBSP1.CLKR serves as the serial shift clock for
the serial port receiver. McBSP1.CLKR is selected when the External Bus
McBSP1.CLKR I/O/Z
Selection Register has 00 in the Serial Port1 Mode bit field or following
H
reset.
Input
MMC1.CMD
SD1.CMD
MMC1 or SD1 command/response is selected when the External Bus
I/O/Z
Selection Register has 10 in the Serial Port1 Mode bit field.
McBSP1 data receive or Secure Digital1 data1. At reset, this pin is
S11
I/O/Z
configured as McBSP1.DR.
McBSP1.DR
McBSP1 serial data receive. McBSP1.DR is selected when the External
I/Z Bus Selection Register has 00 in the Serial Port1 Mode bit field or following
reset.
Input
SD1.DAT1
SD1 data1 is selected when the External Bus Selection Register has 10 in
I/O/Z
the Serial Port1 Mode bit field.
† _{I = Input, O = Output, S = Supply, Hi-Z = High-impedance}
‡ _{BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,}
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
26 SPRS205K
November 2002 − Revised January 2008