TMS320UC5409_16 Datasheet, PDF (51/81 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

Not Recommended For New Designs
TMS320UC5409
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
memory and parallel I/O interface timing (continued)
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
switching characteristics over recommended operating conditions for a parallel I/O port write
(IOSTRB = 0) [H = 0.5 t_c(CO)]^† (see Figure 19)
PARAMETER
td(CLKL-A)
td(CLKH-ISTRBL)
td(CLKH-D)IOW
td(CLKH-ISTRBH)
td(CLKL-RWL)
td(CLKL-RWH)
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to write data valid
Delay time, CLKOUT high to IOSTRB high
Delay time, CLKOUT low to R/W low
Delay time, CLKOUT low to R/W high
th(A)IOW
Hold time, address valid after CLKOUT low
th(D)IOW
Hold time, write data after IOSTRB high
tsu(D)IOSTRBH Setup time, write data before IOSTRB high
tsu(A)IOSTRBL Setup time, address valid before IOSTRB low
† _{Address and IS timings are included in timings referenced as address.}
MIN MAX
0
3
0
3
H−5 H+3
0
3
0
3
0
3
0
3
H−3 H+3
H−3 H+1
H−3 H+3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
td(CLKL-A)
A[19:0]
tsu(A)IOSTRBL
th(A)IOW
td(CLKH-D)IOW
D[15:0]
td(CLKH-ISTRBL)
td(CLKH-ISTRBH)
IOSTRB
td(CLKL-RWL)
th(D)IOW
tsu(D)IOSTRBH
td(CLKL-RWH)
R/W
IS
Figure 19. Parallel I/O Port Write (IOSTRB = 0)
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