TMS320UC5409_16 Datasheet, PDF (44/81 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320UC5409
Not Recommended For New Designs
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
divide-by-two clock option
The frequency of the external reference clock provided at the X2/CLKIN pin can be divided by a factor of two
to generate the internal machine cycle. The selection of the clock mode is described in the clock generator
section.
The external frequency injected must conform to specifications listed in the timing requirements table.
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)]^† (see Figure 13,
Figure 14, and the recommended operating conditions table)
PARAMETER
MIN TYP MAX UNIT
tc(CO)
Cycle time, CLKOUT
10‡ 2tc(CI)
† _ns
td(CIH-CO) Delay time, X2/CLKIN high to CLKOUT high/low
3
6
10 ns
tf(CO)
Fall time, CLKOUT
2
ns
tr(CO)
Rise time, CLKOUT
2
ns
tw(COL)
Pulse duration, CLKOUT low
H−2 H−1
H ns
tw(COH)
Pulse duration, CLKOUT high
H−2 H−1
H ns
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz.
‡ _{It is recommended that the PLL clocking option be used for maximum frequency operation.}
timing requirements (see Figure 14)
MIN MAX UNIT
tc(CI) Cycle time, X2/CLKIN
5
† _ns
tf(CI) Fall time, X2/CLKIN
1 ns
tr(CI) Rise time, X2/CLKIN
1 ns
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz.
X2/CLKIN
tc(CI)
tr(CI)
tf(CI)
CLKOUT
tc(CO)
td(CIH-CO)
tf(CO)
tr(CO)
tw(COH)
tw(COL)
Figure 14. External Divide-by-Two Clock Timing
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