ADC32J42 Datasheet, PDF (51/85 Pages) Texas Instruments – Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters

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ADC32J42, ADC32J43, ADC32J44, ADC32J45
SBAS663A – MAY 2014 – REVISED JUNE 2015
9.3.5.1 JESD204B Initial Lane Alignment (ILA)
The initial lane alignment process is started by the receiving device by asserting the SYNC~ signal. When a logic
high is detected on the SYNC~ input pins, the ADC32J4x starts transmitting comma (K28.5) characters to
establish code group synchronization. When synchronization is complete, the receiving device de-asserts the
SYNC~ signal and the ADC32J4x starts the initial lane alignment sequence with the next local multiframe clock
boundary. The ADC32J4x transmits four multiframes, each containing K frames (K is SPI programmable). Each
multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link
configuration data.
9.3.5.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The ADC32J4x
supports a clock output, an encoded, and a PRBS (2¹⁵ – 1) pattern. These patterns can be enabled via SPI
register writes and are located in address 26h (bits 7-6).
9.3.5.3 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• L is the number of lanes per link,
• M is the number of converters per device,
• F is the number of octets per frame clock period, and
• S is the number of samples per frame.
Table 3 lists the available JESD204B format and valid range for the ADC32J4x. The ranges are limited by the
SERDES line rate and the maximum ADC sample frequency.
Table 3. LMFS Values and Interface Rate
MINIMUM ADC
MAXIMUM ADC
SAMPLING RATE
MAXIMUM
SAMPLING RATE
MAXIMUM
L
M
F
S
(MSPS)
f_SERDES (Mbps)
(Msps)
f_SERDES (GSPS)
MODE
2
2
2
1
15
300
160
3.2
20X (default)
1
2
4
1
10
400
80
3.2
40X
The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration
can be changed from 20X (default) to 40X by setting the registers listed in Table 4.
LMFS = 2221
LMFS = 1241
Lane DA
Lane DB
Figure 158. JESD Frame Assembly
ADDRESS
2Bh
30h
Table 4. Configuring 40X Mode
DATA
01h
11h
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