ADC32J42 Datasheet, PDF (1/85 Pages) Texas Instruments – Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters

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ADC32J42, ADC32J43, ADC32J44, ADC32J45
SBAS663A – MAY 2014 – REVISED JUNE 2015
ADC32J4x Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters
with JESD204B Interface
1 Features
•1 Dual Channel
• 14-Bit Resolution
• Single Supply: 1.8 V
• Flexible Input Clock Buffer with Divide-by-1, -2, -4
• SNR = 72.2 dBFS, SFDR = 87 dBc at
f_IN = 70 MHz
• Ultralow Power Consumption:
– 227 mW/Ch at 160 MSPS
• Channel Isolation: 105 dB
• Internal Dither
• JESD204B Serial Interface:
– Subclass 0, 1, 2 Compliant up to 3.2 Gbps
– Supports One Lane per ADC up to 160 MSPS
• Support for Multichip Synchronization
• Pin-to-Pin Compatible with 12-Bit Version
(ADC32J2X)
• Package: VQFN-48 (7 mm × 7 mm)
2 Applications
• Multi-Carrier, Multi-Mode Cellular Base Stations
• Radar and Smart Antenna Arrays
• Munitions Guidance
• Motor Control Feedback
• Network and Vector Analyzers
• Communications Test Equipment
• Nondestructive Testing
• Microwave Receivers
• Software-Defined Radios (SDRs)
• Quadrature and Diversity Radio Receivers
3 Description
The ADC32J4x are a high-linearity, ultra-low power,
dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-
to-digital converter (ADC) family. The devices are
designed specifically to support demanding, high
input frequency signals with large dynamic range
requirements. A clock input divider allows more
flexibility for system clock architecture design and the
SYSREF input enables complete system
synchronization. The ADC32J4x family supports
JESD204B interface in order to reduce the number of
interface lines, thus allowing high system integration
density. The JESD204B interface is a serial interface,
where the data of each ADC are serialized and output
over only one differential pair. An internal phase-
locked loop (PLL) multiplies the incoming ADC
sampling clock by 20 to derive the bit clock, which is
used to serialize the 14-bit data from each channel.
The devices support subclass 1 with interface speeds
up to 3.2 Gbps.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADC32J4x
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Performance at f_S = 160 MSPS, f_IN = 10 MHz
(SNR = 72.5 dBFS, SFDR = 92 dBc)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
16
32
48
64
Frequency (MHz)
80
D101
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.