THS4541 Datasheet, PDF (50/62 Pages) Texas Instruments – Fully Differential Amplifier

THS4541
SLOS375 – AUGUST 2014
12 Layout
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12.1 Layout Guidelines
Similar to all high-speed devices, best system performance is achieved with a close attention to board layout.
The THS4541 evaluation module (EVM) shows a good example of high frequency layout techniques as a
reference. This EVM includes numerous extra elements and features for characterization purposes that may not
apply to some applications. General high-speed, signal-path layout suggestions include:
• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, open up both ground and power planes around the capacitive sensitive input and output device
pins. After the signal is sent into a resistor, parasitic capacitance becomes more of a bandlimiting issue and
less of a stability issue.
• Use good, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power pins.
Higher value capacitors (2.2 µF) are required, but may be placed further from the device power pins and
shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that
offer a much higher self-resonance frequency over standard capacitors.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces.
• Higher-speed FDAs, such as the THS4541, include a duplicate of the output pins on the input feedback side
of the larger 16-pin VQFN (RGT) package. This duplication is intended to allow the external feedback
resistors to be connected with virtually no trace length on the input side of the package. Use this layout
approach with no extra trace length on this critical feedback path. The smaller 10-pin, WQFN (RUN) package
lines up the outputs and the required inputs on the same side of the package where the feedback (Rf)
resistors are placed immediately adjacent to the package with minimal trace length.
• The input summing junctions are very sensitive to parasitic capacitance. Connect any Rg elements into the
summing junction with minimal trace length to the device pin side of the resistor. The other side of the Rg
elements can have more trace length if needed to the source or to ground.
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