SM320VC5507-EP Datasheet, PDF(50/108 Page) Texas Instruments

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SM320VC5507-EP Datasheet, PDF (50/108 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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SM320VC5507-EP

SPRS613 â SEPTEMBER 2009

www.ti.com

Table 3-31. I2C Module Registers (1) (continued)

0x3C00

0x3C01

0x3C02

0x3C03

0x3C04

0x3C05

0x3C06

0x3C07

0x3C08

0x3C09

0x3C0A

I2COAR[9:0] (3)

I2CIER

I2CSTR

I2CCLKL[15:0]

I2CCLKH[15:0]

I2CCNT[15:0]

I2CDRR[7:0]

I2CSAR[9:0]

I2CDXR[7:0]

I2CMDR[14:0]

I2CISRC

I2C own address register

I2C interrupt enable register

I2C status register

I2C clock divider low register

I2C clock divider high register

I2C data count

I2C data receive register

I2C slave address register

I2C data transmit register

I2C mode register

I2C interrupt source register

0000 0000 0000 0000

0000 0001 0000 0000

0000 0000 0000 0000

0000 0011 1111 1111

0000 0000 0000 0000

0x3C0B

0x3C0C

I2CPSC

Reserved

I2C prescaler register

0000 0000 0000 0000

0x3C0D

Reserved

0x3C0E

0x3C0F

I2CMDR2

I2CRSR

I2CXSR

Reserved

I2C mode register 2

I2C receive shift register (not accessible to the CPU)

I2C transmit shift register (not accessible to the CPU)

0000 0000 0000 0000

(3) This register must be set by the user. The user may program the I2Câs own address to any value, as long as the value does not conflict

with the I2C addresses of other components connected to the I2C bus.

Table 3-32. Watchdog Timer Registers

WORD ADDRESS

0x4000

0x4001

0x4002

0x4003

WDTIM[15:0]

WDPRD[15:0]

WDTCR[13:0]

WDTCR2[15:0]

(1) Hardware reset; x denotes a âdonât care.â

DESCRIPTION

WD timer counter register

WD timer period register

WD timer control register

WD timer control register 2

RESET VALUE (1)

1111 1111 1111 1111

0000 0011 1100 1111

0001 0000 0000 0000

Table 3-33. USB Module Registers

WORD ADDRESS

DMA CONTEXTS

0x5800

0x5808

0x5810

0x5818

0x5820

0x5828

0x5830

0x5838

0x5840

0x5848

0x5850

0x5858

0x5860

DESCRIPTION

Reserved

DMAC_O1

DMAC_O2

DMAC_O3

DMAC_O4

DMAC_O5

DMAC_O6

DMAC_O7

Reserved

DMAC_I1

DMAC_I2

DMAC_I3

DMAC_I4

Output endpoint 1 DMA context register

Output endpoint 2 DMA context register

Output endpoint 3 DMA context register

Output endpoint 4 DMA context register

Output endpoint 5 DMA context register

Output endpoint 6 DMA context register

Output endpoint 7 DMA context register

Input endpoint 1 DMA context register

Input endpoint 2 DMA context register

Input endpoint 3 DMA context register

Input endpoint 4 DMA context register

RESET VALUE(1) (2)

Undefined

(1) Hardware reset; x denotes a âdonât care.â

(2) The USB module must be brought out of reset by setting bit 2 of the USB Idle Control and Status Register before any USB module

Functional Overview

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