SM320VC5507-EP Datasheet, PDF (41/108 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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REGISTER
AC2H
AC2G
CDP
AC3L
AC3H
AC3G
DPH
MDP05
MDP67
DP
PDP
BK47
BKC
BSA01
BSA23
BSA45
BSA67
BSAC
BIOS
TRN1
BRC1
BRS1
CSR
RSA0H
RSA0L
REA0H
REA0L
RSA1H
RSA1L
REA1H
REA1L
RPTC
IER1
IFR1
DBIER0
DBIER1
IVPD
IVPH
ST2_55
SSP
SP
SPH
CDPH
SM320VC5507-EP
Table 3-19. CPU Memory-Mapped Registers (continued)
WORD ADDRESS
(HEX)
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
DESCRIPTION
Coefficient data pointer
Accumulator 3
Extended data page pointer
Reserved
Reserved
Memory data page start address
Peripheral data page start address
Circular buffer size register for AR[4−7]
Circular buffer size register for CDP
Circular buffer start address register for AR[0−1]
Circular buffer start address register for AR[2−3]
Circular buffer start address register for AR[4−5]
Circular buffer start address register for AR[6−7]
Circular buffer coefficient start address register
Data page pointer storage location for 128-word data table
Transition register 1
Block repeat counter 1
Block repeat save 1
Computed single repeat
Repeat start address 0
Repeat end address 0
Repeat start address 1
Repeat end address 1
Repeat counter
Interrupt enable register 1
Interrupt flag register 1
Debug IER0
Debug IER1
Interrupt vector pointer DSP
Interrupt vector pointer HOST
Status register 2 for C55x
System stack pointer
User stack pointer
Extended data page pointer for the SP and the SSP
Main data page pointer for the CDP
SPRS613 – SEPTEMBER 2009
BIT FIELD
[31−16]
[39−32]
[15−0]
[15−0]
[31−16]
[39−32]
[6−0]
[6−0]
[6−0]
[15−0]
[8−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[6−0]
[6−0]
Copyright © 2009, Texas Instruments Incorporated
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Functional Overview
41