ADS5263_1110 Datasheet, PDF (50/75 Pages) Texas Instruments – Quad Channel 16-Bit, 100-MSPS High-SNR ADC

ADS5263
SLAS760B – MAY 2011 – REVISED OCTOBER 2011
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Large and Small Signal Input Bandwidth
The small signal bandwidth of the analog input circuit is high, around 700 MHz. When using an amplifier to drive
the ADS5263, the total noise of the amplifier up to the small signal bandwidth must be considered.
The large signal bandwidth of the device depends on the amplitude of the input signal. The ADS5263 supports 4
V_PP amplitude for input signal frequency up to 70 MHz. For higher frequencies (>70 MHz), the amplitude of the
input signal must be decreased proportionally. For example, at 140 MHz, the device supports a maximum of 2
V_PP signal and at 280 MHz, it can handle a maximum of 1 V_PP.
Figure 52. FullScale Input Amplitude Across Input Frequency
CLAMP FUNCTION
The 14-bit ADC analog inputs have an integrated clamp function that can be used to interface to a CCD sensor
output. A typical CCD sensor output has three timing phases – a reset phase followed by a reference phase and
the actual picture phase.
The analog inputs of the ADS5263 are clamped to a voltage (V_clamp) decided by an internally generated
CLAMP clock signal. The CLAMP clock signal is high for one ADC clock cycle and low for two cycles. A
high-going signal on SYNC can be used to synchronize the CLAMP clock with the reset phase of the CCD
sensor output.
An equivalent circuit of the input pins and a detailed timing diagram showing the clamp action is shown in
Figure 53.
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