ADS5263_1110 Datasheet, PDF (13/75 Pages) Texas Instruments – Quad Channel 16-Bit, 100-MSPS High-SNR ADC

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ADS5263
SLAS760B – MAY 2011 – REVISED OCTOBER 2011
TIMING REQUIREMENTS⁽¹⁾
Typical values are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, sampling frequency = 100 MSPS, sine wave input clock = 1.5 Vpp
clock amplitude,
C_LOAD = 5 pF⁽²⁾, RL_OAD = 100 Ω⁽³⁾, unless otherwise noted. MIN and MAX values are across the full temperature range T_MIN
= –40°C to T_MAX = 85°C, AVDD = 3.3 V, LVDD = 1.7 V to 1.9 V
PARAMETER
CONDITIONS
MIN TYP MAX UNIT
t_j
Aperture jitter
Wake-up time
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of global power down
220
fs rms
10
μs
60
ADC latency
2 WIRE, 16× SERIALIZATION⁽⁴⁾
Latency of ADC alone, excludes the delay from input clock to
output clock (t_PDI), Figure 5
16
Clock
cycles
t_su
Data setup time
Data valid (5) to zero-crossing of LCLKP
0.23
ns
t_h
Data hold time
Zero-crossing of LCLKP to data becoming invalid⁽⁵⁾
0.31
ns
t_PDI
Clock propagation
delay
Input clock rising edge crossover to output frame clock ADCLKP
rising edge crossover, t_PDI = (t_s/4) + t_delay
6.8 8.8 10.8 ns
Variation of t_PDI
Between two devices at same temperature and LVDD supply
±0.6
ns
LVDS bit clock duty
cycle
Duty cycle of differential clock, (LCLKP-LCLKM)
50%
t_RISE
t_FALL
Data rise time,
Data fall time
Rise time measured from –100 mV to 100 mV,
Fall time measured from 100 mV to –100 mV
10 MSPS ≤ Sampling frequency ≤ 100 MSPS
0.17
ns
t_CLKRISE
t_CLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –100 mV to 100 mV
Fall time measured from 100 mV to –100 mV
10 MSPS ≤ Sampling frequency ≤ 100 MSPS
0.2
ns
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) R_LOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to logic HIGH of 100 mV and logic LOW of –100 mV.
Table 1. LVDS Timing at Lower Sampling Frequencies - 2 Wire, 16× Serialization
SAMPLING FREQUENCY, MSPS
80
65
50
20
SETUP TIME, ns
Min Typ Max
0.47
0.56
0.66
2.7
HOLD TIME, ns
Min Typ Max
0.47
0.7
1
2.8
Table 2. LVDS Timing for 1 Wire 16× Serialization
SAMPLING FREQUENCY, MSPS
65
50
40
20
SETUP TIME, ns
Min Typ Max
0.15
0.27
0.45
1.1
Clock Propagation Delay
t_PDI = (t_s/8) + t_delay
10 MSPS < Sampling Frequency < 65 MSPS
t_delay, ns
Typ Min Max
6.8 8.8 10.8
HOLD TIME, ns
Min Typ Max
0.31
0.35
0.55
1.4
Copyright © 2011, Texas Instruments Incorporated
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