ADC324X Datasheet, PDF (50/81 Pages) Texas Instruments – The ADC324x are a high-linearity

ADC3241, ADC3242, ADC3243, ADC3244
SBAS671B – JULY 2014 – REVISED MARCH 2015
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External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass
filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The ADC324x has a
typical thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR depending on amount of
external jitter for different input frequencies is shown in Figure 141.
73.0
72.5
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
67.5
67.0
10
Ext Clock Jitter
35 fs
50 fs
100 fs
150 fs
200 fs
100
Input Frequency (MHz)
1000
D00316
Figure 141. SNR vs Frequency for Different Clock Jitter
9.3.3 Digital Output Interface
The devices offer two different output format options, thus making interfacing to a field-programmable gate array
(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using
the serial interface, as shown in Table 3. The output interface options are:
• One-wire, 1x frame clock, 14x serialization with the DDR bit clock and
• Two-wire, 0.5x frame clock, 7x serialization with the DDR bit clock.
INTERFACE
OPTIONS
One-wire
Two-wire
SERIALIZATION
14x
7x
Table 3. Interface Rates
MAXIMUM RECOMMENDED
SAMPLING FREQUENCY
(MSPS)
80
125
BIT CLOCK
FREQUENCY
(MHz)
560
437.5
FRAME CLOCK
FREQUENCY
(MHz)
80
62.5
SERIAL DATA
RATE PER WIRE
(Mbps)
1120
875
9.3.3.1 One-Wire Interface: 14x Serialization
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The
data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at
the rising edge of every frame clock, starting with the MSB. The data rate is 14x sample frequency (14x
serialization).
50
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