ADC324X Datasheet, PDF (48/81 Pages) Texas Instruments – The ADC324x are a high-linearity

ADC3241, ADC3242, ADC3243, ADC3244
SBAS671B – JULY 2014 – REVISED MARCH 2015
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9.3 Feature Description
9.3.1 Analog Inputs
The ADC324x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing
symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP (default) differential input swing.
The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω
termination between INP and INM).
9.3.2 Clock Input
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC324x can be driven by the transformer-
coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in
Figure 136, Figure 137, and Figure 138. See Figure 139 for details regarding the internal clock buffer.
0.1 mF
CLKP
Z_o
0.1 mF
CLKP
Differential
Sine-Wave
Clock Input
R_T
0.1 mF
CLKM
NOTE: R_T = termination resistor, if necessary.
Device
Typical LVDS
Clock Input
Z_o
100 W
0.1 mF
CLKM
Device
Figure 136. Differential Sine-Wave Clock Driving
Circuit
Figure 137. LVDS Clock Driving Circuit
Typical LVPECL
Clock Input
Z_o
0.1 mF
150 W
CLKP
100 W
Z_o
0.1 mF
150 W
CLKM
Device
Figure 138. LVPECL Clock Driving Circuit
48
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