TMS320DM6446_17 Datasheet, PDF (5/227 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
1.3
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
JTAG Interface
Video-Imaging
Coprocessor (VICP)
BT.656,
Y/C,
Raw (Bayer)
System Control
ARM Subsystem
DSP Subsystem
Video Processing Subsystem (VPSS)
Input
Clock(s)
PLLs/Clock
Generator
Power/Sleep
Controller
Pin
Multiplexing
ARM926EJ-S CPU
16 KB
I-Cache
8 KB
D-Cache
16 KB RAM
8 KB ROM
C64x+™ DSP CPU
64 KB L2 RAM
32 KB
L1 Pgm
80 KB
L1 Data
Front End
CCD
Controller
Video
Interface
Resizer
Histogram/
3A
Preview
Back End
On-Screen
Display
(OSD)
10b DAC
Video
Encoder 10b DAC
(VENC) _{10b DAC}
10b DAC
8b BT.656,
Y/C,
24b RGB
NTSC/
PAL,
S-Video,
RGB,
YPbPr
Switched Central Resource (SCR)
Peripherals
Serial Interfaces
EDMA3
Audio
Serial
I²C
SPI
Port
Connectivity
USB 2.0
PHY
VLYNQ
EMAC
With
MDIO
HPI
System
UART
General-
Purpose
Timer
Watchdog
Timer
Program/DataStorage
PWM
DDR2
Mem Ctlr
(16b/32b)
Async EMIF/
NAND/
SmartMedia
ATA/
Compact
Flash
MMC/
SD/
SDIO
Figure 1-1. TMS320DM6446 Functional Block Diagram
Copyright © 2005–2010, Texas Instruments Incorporated
Digital Media System-on-Chip (DMSoC)
5
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